JPS58115683A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To perform high-speed reading operation by multiplying data lines and putting in operation selectively at intervals of one cycle, and thus canceling signals remaining on other data lines while some data line is in use. CONSTITUTION:Memory cells are arranged in a matrix of (m) rows by (n) columns and while (m) couples of bit lines are arranged in a row direction, (n) word lines are arranged in a column direction to constitute a memory device. When a data line couple DLj' are in use one cycle before, a column selection signal Ci for a memory cell to be read is held at a level ''High'' in a new readout cycle and a data line selection signal Fj used one cycle before is also held at the level ''High'' to fetch signals of the memory cells to data line couples DLj other than a data line couple DLj used one cycle before. At this time, a precharge operation signal Cj' is held at the level ''High'' to cancel the signal remaining on the data line DLj used one cycle before. Then, the signals led out to the data line couples DLj are inputted to an output circuit through a connection part.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high speed static memory.

An example of a conventional static memory device is shown in FIG.

Memory cells are arranged in m rows and n columns, and m human line pairs (BLInπ4i j '', 1 +...m
)//n word lines toward Reno J (WLki k =
1,...n) are arranged. The focus line is connected to one data line pair (DI,
, DL), and the input terminal of the output circuit is connected to the data line.

As shown in FIG. 2, the memory cell is composed of four transistors Q to Q40 and two load elements l. Signals from memory cells are read out to data lines via bit lines and multiplexers.

In the conventional asynchronous static memory, a memory cell at an address of 11 is always selected, so that the signal of that memory cell remains read onto the data line.

Therefore, when a new read cycle starts and a memory cell at a different address is selected, the signal from one cycle before remains on the data line, and in order to read the new signal, the remaining signal must be It is necessary to cancel the signal. The operation time required to cancel the remaining signals has been a major cause of slowing down the read operation of the static memory.

The present invention is characterized in that l (≧2) data line pairs are provided and the data lines are switched every cycle to perform a read operation.The purpose of this invention is to read out the signal remaining on the data line from l cycle before. It is also possible to increase the speed by canceling the previous state, and by using a sense amplifier using a flip-flop circuit, which was difficult to introduce in the conventional static memory.

FIG. 3 shows a first embodiment of the present invention, in which memory cells are
Arranged in rows and n columns, Km pairs of pins (BLi,
'ip; t = 1 #-...m), Kn word lines in the column direction (Wk; = 1......
n), l (≧2) data line pairs (DLk, -DL); k = 1, -
・l) and a multiplexer (MUX tj: r-Ig...m) arranged in m rows and 1 columns.

j=1. . . . n) are provided, and each bit line pair (BL
i+Btj i 1 ” 1 *...m) respectively into one multiplexer (MUXll, --, MU
Xili i = 1 e """ m), and each data line pair (DL J , DL y
1J=1.・・・・・・l) respectively into m multiplexers (MUX, j, ・・・MUXmj; j=
1. ......l), and a precharge circuit (pj;j: 1.....) is connected to each data line.
1), and a connecting portion 3 is provided between one data line pair and the output circuit.

As the multiplexer, one using a transfer gate as shown in FIG. 4(a) or one using a differential amplifier circuit as shown in FIG. 4(b) can be used. As a precharge circuit, a circuit using nMO8 shown in Fig. 5(a) or a circuit using nMO8 shown in Fig.
A circuit using pMO8 shown in Figure (b) can be used.

As a control signal, a data line selection signal (FJ ij-
1,...l) and precharge operation signal (G,:
j-1゜...-・l) and column selection signal (C+;
+-1+...m), Gj is "H4gh
”, the precharge circuit operates, and C becomes “High.”
When Fj is ``)Ihigh'', bit line pair BL is selected by multiplexer MUX, .
The data line pair DLj and DL are electrically connected.

The read operation will be explained using the data line pair DLk, DLk. In this case, it is assumed that the data line pair DLj/, DJz was used l cycles ago. In a new read cycle, the column selection signal C1 corresponding to the memory cell to be read is set to "High",
Data line selection signal Fj (j
\j') is set to "High", and the memory cell signal is taken out to the data line pairs DLj, DL, other than the data line pair DLj/, T5qt used one cycle ago. At this time, the precharge operation signal GJ/ is set to “High”.
By doing this, the signals remaining on the data lines DLj and DL used l cycles ago are canceled. Then, the signals taken out from the data line pairs DL, DL, K are inputted to the output circuit via the connection portion.

In this way, data line pairs are sequentially lulked every cycle.
By performing a read operation after +lfi, the data line χ
The signal remaining at 1 can be canceled before the read operation, and the signal inversion time of the data line can be shortened.

FIG. 6 shows a second embodiment of the present invention, in which one sense amplifier (SA J l 3-
1,...l) and a switching circuit 4,
One pair of data lines is connected to a pair of input terminals of two seven amplifiers, each pair of output terminals of one sense amplifier is connected to a pair of input terminals f of one switching circuit, The output terminal pair of the switching circuit 4 is connected to the input terminal pair of the output circuit.

For sense-up, a circuit configured with n MOS shown in FIG. 7(a) or an n MOS shown in FIG. 7(b), ! :
A circuit configured with PMO8 or the like can be used.

In conventional static memories, flip-flop circuits cannot be used as sense amplifiers, but in the present invention, the data lines can be brought into a balanced state before one flush operation, so they can be used. The switching circuit is composed of a transfer gate as shown in Fig. 8, and the output terminal of the sense-up SAj is electrically connected to the input terminal of the output circuit by setting the control signal s to High. In this second embodiment, the operation of sequentially switching the data lines is the same as in the first embodiment; the difference is that after a signal appears on the data line in use, it is connected The output terminal of the sense amplifier is electrically connected to the input terminal of the output circuit by a switching circuit.

In addition, this second embodiment has the same effect as the first embodiment, and also has the effect of being able to amplify minute signals appearing on the data line at high speed by providing a sense amplifier using a flip-flop circuit. There is. With this configuration, the driving force for the output circuit can be increased, so the operating time of the data line and output circuit can be shortened, and the signal amplitude of the bit line electrically connected via the multiplexer can be reduced, so the bit The line signal inversion time can also be shortened.

FIG. 9 shows a third embodiment of the present invention, in which the connection portion of the first embodiment is replaced by one transfer gate controlled by a control signal E and a flip-flop circuit driven by a control signal H1. It is constructed using one sense-up and switching circuit 4, one data line pair is connected to one transfer gate input terminal pair, and one transfer gate output terminal pair is connected to one transfer gate output terminal pair. Connect the output terminals f of one sense amplifier to one pair of input terminals of a switching circuit, and connect the output terminal pair of one sense amplifier to one pair of input terminals of a switching circuit. It is electrically connected to the input terminal pair of the output circuit. As a transfer gate, a circuit using one transistor as a basic gate as shown in Fig. 1O(a) or an n MO as shown in Fig. 1O(b) is used.
S, pMO81 set as the basic gate, etc. can be used.

The operation of sequentially switching the data lines is the same as in the first embodiment, but the difference is that the signal of the data line pair in use appears on the sense-up input terminal pair via the transfer gate, and then The method is to electrically disconnect the sense-up and sense-up, then drive the sense-up, and electrically connect the output terminal pair of the sense-up to the input terminal pair of the output circuit by a switching circuit. FIG. 11 shows an example of a clock waveform when this embodiment is operated.

The third embodiment described above has the same effect as the first and second embodiments, and furthermore, since the data line with a large load capacitance is disconnected from the sense amplifier when driving the sense amplifier, high-speed sense amplifier operation is possible. It has the effect of becoming.

As explained above, data lines are multiplied by l (≧2) and
By switching between cycles, signals remaining on other data lines can be canceled out while one data line is being used, thereby enabling high-speed read operations. Furthermore, since sufficient time can be secured to bring the data lines into an equilibrium state before the read operation, a flip-flop circuit, which has been difficult to introduce in the past, can be used for the sense amplifier, thereby enabling high-speed read operations.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional static memory, Fig. 2 is a circuit diagram of a memory cell, Fig. 3 is a block diagram of a first embodiment of the present invention, and Figs. 5(a) and 5(b) are circuit examples of the precharge circuit, FIG. 6 is the second embodiment of the present invention, and FIG. 7(a>
, (b) is a circuit example of a sense amplifier, FIG. 8 is a circuit example of a switching circuit, FIG. 9 is a third embodiment of the present invention, and FIG.
L (b) is a circuit example of a transfer gate, No. 1117
1 is an example of a clock waveform in the third embodiment. CELI-, l+ CELL, □, ~, CELL,
,. ---)L MoIJ cell, (st,,,'ii
dirt), (BL2.j also), ~, (BL,, ti
L,,'-)・・・・・・・・・Hino) line pair, WL,,W
L2. ~． WIJn・・・・・・Word line,
MtJX, MUX, ~1MUX11...
...Multiple 11 12 Recreation, (DL,, 膓), (DL2. DID
'2), ~, (DL4゜DL z)...
...Data line pair, P P ~, Pl...Song...I
I 21 Precharge circuit, SA,, SA2. ~． SAl
......Sense amplifier, TG,, TG2
．． ~． TGl... River transformer 7-r gate, F,, F2. ~． Fl ・・・・・・・・・
Data line selection signal, G G -, G, <...
・・・Precha+1 21 Single circuit drive signal, C,, C2, ~, Cm...
...Colano, selection signal, 1(,,H2,~,Hl・
......Sense amplifier drive signal, S,, S2
．． ~． Sl......Switching circuit control 1 signal, El, E21~. El・・・・・・・・・
Transfer gate control signal, Q, ~QIf' Q
+5~Q20I Q23~Q28. Q37. Q38...
・・・・・・N-channel field effect transistor,
Q1□” 131 Q14”21e Q2□, Q2.
~Q34゜Q391 Q40...P-channel field effect transistor (arrow in the figure indicates P-channel MO8), Q351
Q36...N-channel or P-channel field effect transistor. (0) Figure 7(b) 1.7-- ----LL LLI Z C
D-” Procedural amendment (method) % formula % [ (1 ; 3 Person making the amendment/Relationship with the 1 yen item Applicant 1) 1.11 1-1-6 Uchisaiwai-cho, Chiyoda-ku, Tokyo? , fl, (422) Nippon Telegraph and Telephone Public Corporation representative,
and Tsune Sadato, Episode 11 03
(43])8111+l; wodaino,)5 Procedure supplement 1
1 Yo Directive with IJ April 911, 1981 (Shipping 11, 4J4, 1982)
2711) (), Supplement 11: The number of inventions increases by .
O Figure 10 (.) (b) X joint end + I X force field 2

Claims (1)

[Claims] (Re) Memory cells are arranged in m rows and n columns, and m hint line pairs (BLi, BLi i i ” 1 +
'2. ===1 m), and in a memory device with n word lines arranged in the column direction (1, 21, . . . , n) in the column direction, l (≧2) data line pairs ( DLj,
D quality; j=1.2.・Song, l) and a multiplexer (MUXB iI = Ia 2r ” arranged in m rows x 1 column)
””p ms J:=l, 2+...song, l
), and each of the hint line pairs is connected to one multiplexer (MTJXi+, -, MUXili i = 1
+ 2 + =-, m) input terminal pairs, and each data line pair is connected to m multiplexers (M
UX+J,...song/MU-Xylj 1j=1.2
．． A precharge circuit (Pjij=1.2...mountain, l) that is connected to the output terminal pair of the data line pair and becomes active only when the data line pair is not used is connected to the output terminal pair of the data line pair (1)''fl
A memory device characterized in that a connection portion is provided for each data line pair and provided between one data line pair and an output circuit. (2) 1 using a flip-flop circuit for the connection part
It is configured using 2 sense amplifiers and a switching circuit, 2 data line pairs are connected to each input terminal pair of 1 sense amplifier, and 1 sense amplifier output terminal pair is connected to 1 sense amplifier output terminal pair, respectively. Claim (1) characterized in that the output terminal pair of one sense amplifier is selected by a switching circuit and electrically connected to the input terminal pair of the output circuit. Memory device as described in section. (3) The connection section is constructed using one transformer 7 agate, one sense amplifier using a flip-flop circuit, and a switching circuit, and one data line pair is connected to one transfer gate input. Connect each pair of output terminals of one transfer gate to a pair of input terminals of one sense amplifier, and connect each pair of output terminals of one sense amplifier to one pair of input terminals of a switching circuit. A memory circuit as claimed in claim (1), characterized in that the output terminal pair of one sense amplifier is selected by a switching circuit and electrically connected to the input terminal pair of the output circuit. Place.