JPS62121986A - Memory circuit - Google Patents

Abstract

PURPOSE:To shorten a time necessary for shifting from a write action to a read one by connecting a pull-up equalizer with a P-channel transistor and an N-channel transistor between a pair of data lines. CONSTITUTION:When the operation is shifted from a write state to a read one, the voltages of the data lines 10 and 11 are boosted by a pull-up circuit formed with N-channel transistors 39 and 40 and a pull-up circuit formed with P-channel transistors 36 and 37. The equalizer N-channel transistor 41 drops the voltage of the data line 10 or 11 to which data at level H is transmitted. When the data lines 10 and 11 attain the prescribed voltages, the transistors 39-41 are turned off, and the transistors 36 and 37 boost the voltages of the data lines 10 and 11. Accordingly the data line when the operation is shifted from a write state to a read one is instantaneously boosted to shorten the shifting time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a static type memory circuit, and particularly to shortening the transition time from a read operation to a write operation.

[Summary of the invention]

This invention provides a memory circuit in which reading and writing are performed using a common data line, and when transitioning from a write operation to a read operation, a P-channel MO
The transition time from read operation to write operation is shortened by raising the voltage of the data line using a first equalization circuit made up of S transistors and a second equalization circuit made up of N-channel λ40S transistors. It was designed to do so.

[Conventional technology]

FIG. 3 shows an example of the configuration of the main parts of a static RAM (random access memory) using conventional MO3I transistors.

In FIG. 3, 51 indicates a memory cell, and a plurality of memory cells 51 are two-dimensionally arranged in a matrix. Each memory cell 51 is composed of a flip-flop circuit of MOS transistors whose inputs and outputs are cross-connected, and MO3I-transistors for gates for inputting and outputting data are connected to both ends of this flip-flop circuit. ing.

Memory cells 51 arranged in the row direction share a common word line 52.
connected to. This word line 52 is connected to an X decoder (not shown), and a row address is specified.
When one word line 52 is designated, the MOS transistor for the gate of the memory cell 51 in the row corresponding to this word line 52 is turned on.

The memory cells 51 arranged in the column direction have a common pair of bits! 53 and bit line 54.

One ends of bit line 53 and bit line 54 are connected to the sources of load MOS transistor 55 and MO3I-transistor 56, respectively. N-channel MOS transistors are used as the MOS transistors 55 and 56. The drains of the MOS transistor 55 and the MOS transistor 56 are at t.
a is connected to a power supply terminal 57 of voltage VDD (for example, 5V). MOS transistor 55 and MOS transistor 5
6 are connected in common, and this connection point is connected to a power supply terminal 57.

The other ends of the bit line 53 and bit vA54 are connected to a switching MOS transistor 58 and an MO3I transistor 5.
They are connected to the drains of 9, respectively. MOS transistor 5
8 and MOS transistor 59, N-channel transistors are used. MOS transistor 58 and MO
The gates of the S transistors 59 are commonly connected, and a column signal input terminal 74 is led out from this connection point.

The sources of the MOS transistor 58 and the MOS transistor 59 are connected to the sources of the load MO3 transistor 7 and the MOS transistor 66 via the data line 60 and the data line 60, respectively, and the sources of the MOS transistor 58 and the MOS transistor 59 are connected to the sources of the load MO3 transistor 7 and the MOS transistor 66, respectively.
MOS transistor 62 and MOS transistor 62 provided between
Connection point of series connection of transistor 3 and power supply terminal 57
MOS transistor 64 and M provided between G and ground
OS Connected to the connection point of the series connection of transistor 5. The sources of the MOS transistor RO 6 and the MO3+- transistor 7 are connected to a non-inverting input terminal and an inverting input terminal of a sense amplifier 68, respectively. As the MOS transistor 6 and the MOS transistor 67, N-channel ones are used. MOS transistor 66 and MO
3I-The drain of transistor 7 is connected to power supply terminal 57. MOS transistor ro 6 and MOS transistor 6
7 gates are commonly connected, and an input terminal 75 for write enable signal pressure is derived from this connection point.

The gate of MO3I-transistor 2 and the gate of MOS transistor 65 are commonly connected, and this connection point is connected to the output terminal of NOR gate 7o.

The gate of the MOS transistor 63 and the gate of the MO3I transistor 4 are commonly connected, and this connection point is connected to the output terminal of the NOR gate 69. One input terminal of NOR gate 69 and NOR gate 7o is connected to input terminal 71 for each write enable signal. NOR gate 7
The other input terminal of the NOR gatero 9 and the other input terminal of the NOR gatero 9 are connected through an inverter 73. A connection point between the other input terminal of NOR gate 70 and inverter 73 is connected to data input terminal 72 .

At the time of writing, the write enable signal pressure supplied to the terminal 71 and the terminal 75 is set to a low level. As a result, the data supplied to the data input terminal 72 is
- The memory cell 51 is connected to the transistor 58, the MOS transistor 59, the bit line 53, and the bit line 54, respectively.
is supplied to the memory cell 51, and data is written into the memory cell 51.

That is, when the write enable signal pressure supplied to the terminal 71 becomes low level, the NOR gate 69 and the NOR gate 70 open, and the input data supplied to the data input terminal 72 is taken out via the NOR gate 69 and the NOR gate 70. It will be done. The NOR gate 69 has an inverter 7
Since the inverted data is supplied through the NOR gate 69 and the data from the input terminal 72 is supplied to the NOR gate 70, normal rotation data is output from the NOR gate 69, and the NOR gate 69 outputs normal rotation data.
Inverted data is output from OR gate 70. N
When the output of OR gate 69 is at high level, MO3I-
The transistor 3 and the Mos transistor 64 are turned on,
When the output of the NOR gate 70 is high level, the MOS
Transistor 62 and MOS transistor 65 are turned on. Therefore, when the input data is high level, M
The connection point between the OS transistor 64 and the MOS transistor 5 becomes low level, and the MOS transistor 62 and MO
The connection point of the S transistor 63 becomes high level. When the input data is low level, the MOS transistor 64
The connection point between MOS transistor 62 and MOS transistor RO 5 becomes high level, and the connection point between MOS transistor 62 and MOS transistor RO 3 becomes low level.

A column signal is supplied to the terminal 74 from a Y decoder (not shown). When this column signal becomes high level,
MOS transistor 58 and MOS transistor 5
9 is turned on, and one memory cell 51 is selected. Outputs from the connection point between the MOS transistor 62 and the MOS transistor 3 and the connection point between the MOS transistor 64 and the MOS transistor 5 are supplied to the memory cell 51 via the selected bit line 53 and bit vA54, respectively.

At the time of reading, the write enable signal supplied to the terminals 75 and 71 is set to high level, and the load MOS transistors 66 and 67 are turned on.

A word line 52 is selected by an X decoder (not shown), all memory cells connected to this word line 52 are activated, and a predetermined pair of pins H' are selected from a Y decoder (not shown). A high level column signal for i53 and bit line 54 is supplied to terminal 74, and MO
S transistors 58 and 59 are turned on. If the MOS transistor connected to the bit line 53 of the flip-flop (not shown) in the memory cell 51 is in an on state, the data line 61 . Selection MO3 transistor 58 and bit line 53
A data line current ■ flows through the memory cell 51 through the path. will flow in. In addition, the load MO3I-transistor 55 connected to one end of the bit line 53 has a power supply voltage V at its gate.
DD is supplied and is in the on state, and a bit line current I flows to the memory cell 51 through this MO3I transistor 55.

will flow in. The sum of this bit line current (8) and the data line type ?n ID described above becomes the sink current (2) of the memory cell 51.

On the other hand, a MOS transistor (not shown) connected to the bit line 54 in the memory cell 51 is in an off state, and no current flows into the memory cell 51 from the bit line 54 and the data line 60.

Therefore, the voltage v of the bit line 53 and the bit line 54,
3 and VSa are different, and these two different potentials are supplied as information of the desired memory cell 51 to the pre-sense amplifier 68 through the data line 60 and data vA61.

The difference signal between the input signals is amplified and supplied to the inverter 76.

For example, when the power supply voltage VDD is 5■, (the higher one)
The voltage VS4 of the bit line 54 is MO3I-transistor 5
6 threshold voltage V th (jfA>0.7
V) and the substrate effect ΔVth (about 1.IV), it becomes quite low, for example, about 3.2V. Furthermore, when the sink current 8 of the memory cell 51 is, for example, 100 μ8, the voltage VS3 of the bit line 53 is slightly lower than VS4 due to the voltage effect within the MOS transistor 55.
For example, it is about 2.9V.

Further, the voltages V6° and V&I of the data line 60 and the data line 61 are respectively V5. and V
It becomes approximately equal to Sa.

However, if the power supply voltage VD11 drops to, for example, about 3V due to an overload or the like, the voltages V6° and V61 of the data line 60 and data line 61 drop to about 1.5V. This value is too low as the input voltage of the pre-sense amplifier 68, so the read pre-sense amplifier 68
There was a problem that 8 stopped working.

Further, as mentioned above, for example, the voltages 6° and 2h1 of both data lines 60 and 61 and the voltages VS3 and VSa of both bit lines 53 and 54 are approximately equal to each other.
Drain-source voltage of MO5 transistors 58 and 59 for column selection. becomes extremely small, and these M
The driving ability of O5I-transistors 58 and 59 is reduced. Then, each area of the selection MO3 transistors 58 and 59 and the MOS transistors 6 and 67 is bit! Even if the area of the driving MOS transistors 55 and 56 is increased to, for example, four times, a large data line current cannot flow, resulting in a problem that high-speed reading cannot be performed.

Furthermore, the junction capacitance of column selection MOS transistors 58 and 59 becomes the stray capacitance of data line 60 and data line 61, respectively.For example, in a memory with a capacity of 64 bits,
The number of columns is 256, and a considerably large stray capacitance is added to the data line 60 and data line 61. Moreover, as mentioned above, in this memory, the drain-source voltage V6S of the MOS transistors 58 and 59 is low, so the junction capacitance thereof is large, and there is a problem that high-speed driving of the data lines 60 and 61 is hindered. .

Therefore, as shown in FIG. 4, the applicant of the present application has proposed a memory circuit in which the load circuit for data line 60 and data line 61 is composed of P-channel MOS transistors 85, 86, and 87. In other words, data line 6
0 and data line 61, the drains of P channel MO3 transistors 86 and 87 are connected to
A diode-connected P-channel MO3I transistor 85 is inserted between the sources of the transistors 86 and 87 and the power supply terminal 57.

In the case of reading, the write enable signal supplied to the terminal 75 is set to a low level and is supplied to each gate of the load MOS transistors 86 and 87, and both MO3 transistors 86 and 87 are turned on. Since their operating point is chosen in the triode region, both MO5 transistors 86 and 87 behave as resistors, as shown in the equivalent circuit in FIG.

Therefore, by using P-channel MOS transistors 86 and 87 as loads and eliminating the substrate effect Δ■th, when the power supply voltage VOO is 5V, the data line 6
0 and the voltage V of the data line 61. and V&I are approximately 3 each.
．． 9v and about 4. Increased to IV.

Therefore, as mentioned above, the power supply voltage V. For example, even if the voltage drops to about 3V, both data vA60.61
The voltage is maintained at about 2V, and the read amplifier operates stably.

Also, the voltages on both data lines 60 and 61 are the same as those on both bit lines 53.
Since the voltage is about 1v higher than the voltage of 54, the selection M
The drain-source voltage v0 of the OS transistors 58 and 59 increases, their driving capability increases, a large data line current can flow, and as a result, high-speed reading becomes possible. Furthermore, the selection MOS transistor 5
Since the VDS of data lines 8 and 59 increases, their junction capacitance decreases, and the stray capacitance of both data lines 51 and 52 decreases, contributing to high-speed reading.

[Problem that the invention seeks to solve]

However, as described above, the data line 60 and the data line 61
voltage V,. and V61 at about 3.9v and about 4.1v, respectively.
By increasing the value v, a problem arises in that the time required to transition from a write operation to a read operation becomes longer. In other words, during a write operation, data &? The voltages V6G and v of the data line 160 and the data line 61 have a high level of approximately 3.2V and a low level of approximately 0.3V. When transitioning from a write operation to a read operation, the data 'IIA60 and the voltage V of the data line 61 during this write. and V61 when reading from about 0.3v and about 3.2v, respectively, the voltage V of the data line 60 and the data line 61,
. and ■6. Approximately 3.9■ and approximately 4. Must be raised to IV. If the voltages Vh0 and V61 of the data line 60 and the data line 61 during reading are increased in this way, the voltages Vh0 and V61 of the data line 60 and the data line 6 during writing are increased.
The voltage difference between the voltage (1) and V&l becomes large, and it takes a long time to read (recovery) immediately after i-number of rows from a write operation to a read operation.

Therefore, an object of the present invention is to provide a memory circuit that can shorten the transition time from a write operation to a read operation and can speed up ride recovery.

[Means for solving problems]

This invention provides a memory circuit in which reading and writing are performed using a common data line, in which a P-channel MOS is connected between a pair of data 749110.11.
First pull-up circuit 3 composed of transistors
6.37 and a first equalization circuit 38 composed of a P-channel MO3 transistor, and an N-channel MO3 transistor.
This memory circuit is characterized in that it includes second pull-up circuits 39 and 40 made up of OS transistors and a second equalization circuit 41 made up of N-channel MOS transistors.

[Effect]

When transitioning from the write state to the read state, the N-channel MOS transistors 39 and 40 and the MO3I-transistor 41 are turned on, and the voltages of the data lines 10 and 11 are raised to a predetermined level. When the voltage of the data line 10 and the data line 11 reaches, for example, 3.2■, M
OS transistor 39.40 and MOS transistor 4
1 is in the off state. For example, if the voltage of the data line 11 is 3.
After reaching 2V, the data &? 111 is raised to a predetermined value.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention.

In FIG. 1, 1 indicates a memory cell, and a plurality of memory cells 1 are two-dimensionally arranged in a matrix. Each memory cell 1 has an M cell whose input and output are cross-connected.
It is composed of a flip-flop circuit of OS transistors, and gate MOS transistors for inputting and outputting data are connected to both ends of the flip-flop circuit.

Memory cells 1 arranged in the row direction are connected to a common word line 2. This word line 2 is connected to an X decoder (not shown)
When a row address is specified and one word line 2 is specified, the MOS l-transistor for the gate of the memory cell 1 in the row corresponding to this word line 2 is turned on.

The memory cells 1 arranged in the column direction are connected to a common pair of bit lines 3 and 4. One ends of bit line 3 and bit line 4 are connected to the sources of load MO5 transistor 5 and MOS transistor 6, respectively. N-channel MOS transistors are used as the MOS transistors 5 and 6. The drains of the MOS transistor 5 and the MOS transistor 6 are connected to the power supply terminal 7 of the power supply voltage VDD (for example, 5V).
connected to. The gates of MOS transistor 5 and MOS transistor 6 are commonly connected, and this connection point is connected to power supply terminal 7.

The other ends of the bit line 3 and bit line 4 are switching MOs.
3 transistor 8 and the drain of MOS transistor 9, respectively. As the MOS transistor 8 and the MOS transistor 9, N-channel transistors are used. The gates of MOS transistor 8 and MOS transistor 9 are commonly connected, and a column signal input terminal 24 is led out from this connection point.

Data line 11 and data line 10 are connected to the sources of MOS transistor 8 and MOS transistor 9, respectively.

Between the data line 10 and the data line 11, a P channel M
A pull-up circuit and an equalization circuit made up of O3 transistors 36, 37, and 38 and a pull-up circuit and equalization circuit made up of N-channel MOS transistors 39, 40, and 41 are connected.

That is, the source of the P-channel MO5I-transistor 35 is connected to the power supply terminal 7, the gate and drain of the MOS transistor 35 are commonly connected, and this connection point is connected to the sources of the P-channel MO3 transistors 36 and 37. The gates of the MOS transistors 36 and 37 are commonly connected, the terminal 25 is led out from this connection point, and this connection point is also connected to the gate of an equalizing MOS transistor 38 provided between the data line 10 and the data line 11. connected to. MO5I - transistors 36 and 3
The drains of 7 are connected to data line 10 and data line 11, respectively.

0M0S transistor 39 whose drains are connected to power supply terminal 7 of N-channel MOS transistors 39 and 40;
and 40 are commonly connected, and the terminal 28 is led out from this connection point, and this connection point is connected to the equalizing N-channel MOS transistor 41 provided between the data line lO and the data line 11. connected to the gate.

The sources of MOS transistors 39 and 40 are connected to data line 1
0 and data line 11.

Further, a data line 11 is connected to a connection point of a series connection of an MO5I transistor 12 and a MOS transistor 13, which are provided between the power supply terminal 7 and the ground. The data ilO is connected to the MOS transistor 14 and M provided between the power supply terminal 7 and the ground.
It is connected to the connection point of the series connection of the OS transistors 15.

The gates of MOS transistor 12 and MOS transistor 15 are commonly connected, and this connection point is connected to the output terminal of NOR gate 20.

The gate of MO3I-transistor 13 and the gate of MOS transistor 14 are commonly connected, and this connection point is connected to the output terminal of NOR gate 19. One input terminal of NOR gate 19 and NOR gate 20 is connected to terminal 21 . The other input terminal of NOR gate 20 and the other input terminal of NOR gate 19 are connected via inverter 23.

A connection point between the other input terminal of NOR gate 20 and inverter 23 is connected to data input terminal 22 .

When the chip enable signal C is at a low level and the write enable signal is at a high level, a low level is supplied to the terminal 25, a high level is supplied to the terminal 28, and a high level is supplied to the terminal 21. Transition from write state to read state.

As described above, the voltages v1 and Vl of the data line 10 and data line ll in the write state are equal to the power supply voltage VD1.
1 is 5V, the threshold voltage Vth is 0°7VS, and the substrate effect ΔVth is 1.1V, they are about 0.3V and about 3.2V, respectively. Therefore, when a high level is supplied to the terminal 28, first, the MOS transistor 39.4
0 and the equalizing MoS transistor 41 are turned on. Since the MOS transistors 39 and 40 are N-channel MOS transistors, when the MO3I transistors 39 and 40 are turned on, the voltage V of the data line 10 and the data line 11 is increased. and V, is 3゜2
It can be raised to v. Also, since the equalizing MOS transistor 41 is turned on, the bit line 10 and the pin H1
The voltage difference between ll is reduced.

Note that if the equalizing MO5 transistor 41 drops too much from one of the high-level data lines 10 or data &111, the bit lines 3 and 4 will be affected, which may cause malfunction. Therefore, the size of the MOS transistor 41 needs to be set optimally.

When the voltages VIO and V of the data line IO and the data line 11 are raised to 3.2V, the MOS transistor 3
9.40 and MOS transistor 41 are turned off.

At this time, since a low level is being supplied to terminal 25,
MOS transistors 36 and 37 and MOS transistor 38 are in an on state. After the voltages Vll+ and Vll of the data line 10 and the data line 11 are raised to 3.2V, the P-channel MOS transistors 37 and 36
Therefore, the voltage Vl of data '4M10 and data line ll
(1 and V are raised to 4V and 3.7V, respectively.

Note that the equalizing MO3 transistor 38 is provided to limit the amplitudes of the data line 10 and the data line 11. By providing the equalizing MO3I-transistor 38, the data inversion time is shortened.

In this way, when the data lines IO and data ill transition from the write state to the read state, the data lines IO and data ill are connected to the pull-up circuit consisting of the N-channel MO3I transistors 39 and 40 and the P-channel MOS transistors 36 and 37.
It is pulled up by a pull-up circuit consisting of. That is, in FIG. 2, when transitioning from the write state to the read state, between times t and -wt, the pull-up circuit consisting of MOS transistors 39 and 40 and the pull-up circuit consisting of MOS transistors 36 and 37,
Data line 10 and data f#111 are pulled up.

Furthermore, the equalizing MOS transistor 4I pulls down one of the data lines 10 or 11 to which high-level data is transmitted. Voltage V of data line 10 and data f%ill. And at time tz to Es when Vll reaches 3.2V, N-channel MOS transistors 39 and 40 and MOS transistor 41 are turned off.

Then, the voltages v1° and V of the data line 10 and the data line 11 are pulled up by the MOS transistors 36 and 37, and a transition can be made to the read state from time t.

〔Effect of the invention〕

According to the present invention, when transitioning from a write state to a read state, the voltage of the data line is applied to the first puller knob circuit formed by a P-channel MO3 transistor and the second puller knob circuit formed by an N-channel MOS transistor. It is pulled up by the up circuit. N channel M
The second pull-up circuit constituted by an OS transistor is turned off when the voltage of the data line is pulled up to a predetermined value. As a result, when transitioning from a write state to a read state, the voltage of the data line is instantly raised, and the time required to transition from a write operation to a read operation is shortened.

[Brief explanation of drawings]

Fig. 1 is a connection diagram of an embodiment of this invention, Fig. 2 is a waveform diagram used to explain an embodiment of this invention, Fig. 3 is a connection diagram of an example of a conventional memory circuit, and Fig. 4 is a conventional FIG. 5 is an equivalent circuit diagram used to explain the conventional memory circuit. Explanation of main symbols in the drawings 1: Memory cell, 3.4: Bit line. to, 1i: data line, 36.37: P-channel MOS transistor for pull-up. 38: P-channel MO3 transistor for equalization, 39.40 N-channel MO for nibble up
S transistor, 41: N-channel MOS transistor for equalization. Agent Patent Attorney Masaaki Sugiura Figure 5 IF type Surface Figure 2 Figure 3

Claims (1)

[Claims] In a memory circuit in which reading and writing are performed using a common data line, a first pull-up circuit constituted by a P-channel MOS transistor and a P-channel MOS transistor between the pair of data lines. A first equalization circuit made up of transistors, and a second pull-up circuit made up of N-channel MOS transistors and N-channel MOS.
A memory circuit characterized in that a second equalization circuit made up of transistors is arranged.