JPS58114255A - デ−タ処理装置におけるレジスタ退避処理方式 - Google Patents

デ−タ処理装置におけるレジスタ退避処理方式

Info

Publication number
JPS58114255A
JPS58114255A JP56215499A JP21549981A JPS58114255A JP S58114255 A JPS58114255 A JP S58114255A JP 56215499 A JP56215499 A JP 56215499A JP 21549981 A JP21549981 A JP 21549981A JP S58114255 A JPS58114255 A JP S58114255A
Authority
JP
Japan
Prior art keywords
register
csect
program
processing
abend
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56215499A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6311703B2 (enExample
Inventor
Yoshihiro Tsurumaki
鶴巻　良弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56215499A priority Critical patent/JPS58114255A/ja
Publication of JPS58114255A publication Critical patent/JPS58114255A/ja
Publication of JPS6311703B2 publication Critical patent/JPS6311703B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
JP56215499A 1981-12-28 1981-12-28 デ−タ処理装置におけるレジスタ退避処理方式 Granted JPS58114255A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56215499A JPS58114255A (ja) 1981-12-28 1981-12-28 デ−タ処理装置におけるレジスタ退避処理方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56215499A JPS58114255A (ja) 1981-12-28 1981-12-28 デ−タ処理装置におけるレジスタ退避処理方式

Publications (2)

Publication Number Publication Date
JPS58114255A true JPS58114255A (ja) 1983-07-07
JPS6311703B2 JPS6311703B2 (enExample) 1988-03-15

Family

ID=16673400

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56215499A Granted JPS58114255A (ja) 1981-12-28 1981-12-28 デ−タ処理装置におけるレジスタ退避処理方式

Country Status (1)

Country Link
JP (1) JPS58114255A (enExample)

Also Published As

Publication number Publication date
JPS6311703B2 (enExample) 1988-03-15

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