JPS5811341U - PLL synthesizer circuit - Google Patents
PLL synthesizer circuitInfo
- Publication number
- JPS5811341U JPS5811341U JP10591181U JP10591181U JPS5811341U JP S5811341 U JPS5811341 U JP S5811341U JP 10591181 U JP10591181 U JP 10591181U JP 10591181 U JP10591181 U JP 10591181U JP S5811341 U JPS5811341 U JP S5811341U
- Authority
- JP
- Japan
- Prior art keywords
- low
- pass filter
- output
- controlled oscillator
- voltage controlled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例の回路ブロック図、第２図、第３図ａ、
ｂは同上の動作説明図、第４図は本考案の一実施例
の回路プロＹり図、第５図は同上の要部の具体回路図、
第６図は同上を用いたワイヤレスインタホーンの回路ブ
ロック図であり、１は位相比較器、２は第１のローパス
フィルタ、３はバッファ増幅器、４は電圧制御発振器、
６はプログラマブルデイバイダ、ｆＳは基準周波数、ｆ
ｏは出力周波数である。
２
１
３ ５ ４Fig. 1 is a circuit block diagram of a conventional example, Fig. 2, Fig. 3 a,
b is an explanatory diagram of the same operation as above, Fig. 4 is a circuit diagram of an embodiment of the present invention, Fig. 5 is a specific circuit diagram of the main part of the same as above,
FIG. 6 is a circuit block diagram of a wireless interphone using the same as above, in which 1 is a phase comparator, 2 is a first low-pass filter, 3 is a buffer amplifier, 4 is a voltage controlled oscillator,
6 is a programmable divider, fS is a reference frequency, f
o is the output frequency. 2 1 3 5 4
Claims (1)
周するプログラマブルデイバイダと、該プログラマブル
デイバイダの出力周波数と基準周波数との位相を比較す
る位相比較器と、該位相比較器の比較出力を入力する第
１のローパスフィルタと、バッファ増巾器を介して第１
のローパスフィルタの出力を入力する第２のローパスフ
ィルタとを有し、該第２のローパスフィルタの出力で電
圧制御発振器の発振周波数を制御するようにして成′る
ＰＬＬシンセサイザ回路。A voltage controlled oscillator, a programmable divider that divides the output frequency of the voltage controlled oscillator, a phase comparator that compares the phase between the output frequency of the programmable divider and a reference frequency, and a comparison output of the phase comparator. A first low-pass filter inputs and a first low-pass filter input through a buffer amplifier.
a second low-pass filter inputting the output of the low-pass filter, and the oscillation frequency of a voltage controlled oscillator is controlled by the output of the second low-pass filter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10591181U JPS5811341U (en) | 1981-07-15 | 1981-07-15 | PLL synthesizer circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10591181U JPS5811341U (en) | 1981-07-15 | 1981-07-15 | PLL synthesizer circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5811341U true JPS5811341U (en) | 1983-01-25 |
Family
ID=29900427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10591181U Pending JPS5811341U (en) | 1981-07-15 | 1981-07-15 | PLL synthesizer circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5811341U (en) |
-
1981
- 1981-07-15 JP JP10591181U patent/JPS5811341U/en active Pending
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