JPS58112347A - Package for integrated circuit - Google Patents

Package for integrated circuit

Info

Publication number
JPS58112347A
JPS58112347A JP21052881A JP21052881A JPS58112347A JP S58112347 A JPS58112347 A JP S58112347A JP 21052881 A JP21052881 A JP 21052881A JP 21052881 A JP21052881 A JP 21052881A JP S58112347 A JPS58112347 A JP S58112347A
Authority
JP
Japan
Prior art keywords
integrated circuit
package
support
input
sic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21052881A
Other languages
Japanese (ja)
Inventor
Masahiro Sugimoto
杉本　正浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21052881A priority Critical patent/JPS58112347A/en
Publication of JPS58112347A publication Critical patent/JPS58112347A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Abstract

PURPOSE:To make it difficult for heat-caused distortion to affect an IC accommodated in a package, to improve precision in a manufacturing process, and to furnish the IC with a better insulating feature by a method wherein a support for an IC is composed of beta-SiC so that the IC substrate approximates beta-SiC in thermal performance. CONSTITUTION:The surdip-type IC package is similar in structure to conventional ones but is different from them in that it uses beta-SiC for a support 1 and a cap 7. The input and output terminals 10 of an IC substrate 9 are connected to pins 13 and 14 via leads 11 and 12 and an end of each of the pins 13 and 14 is securely bonded to the package by a bonding agent 15 represented by glass applied between the ring-shaped end surface 6 of the support 1 and a ring-shaped end surface 8 of the cap 7. The lower surface of the IC substrate 9 is fixed to the inner surface of a beta-SiC vessel 1, by an Au, Pd/Au, or Cu thick film subjected to baking for the constitution of a surdip-type package for an IC.

Description

【発明の詳細な説明】 （１）０発明の技術分野 本発明はパッケージの支持体等にβ−シリコンカーバイ
トを用いた集積回路用パッケージに関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to an integrated circuit package using β-silicon carbide for the package support and the like.

（２）、技術の背景 最近の大規模集積回路（ＬＳＩ）乃至超ＬＳＩは４〜５
箇角チツプサイズから１５〜２０鯛角チツプサイズの半
導体基板が用いられる趨勢にるる。(2), Technology background The recent large-scale integrated circuits (LSIs) and very large-scale integrated circuits (LSIs) are 4 to 5
There is a trend to use semiconductor substrates with chip sizes ranging from 15 to 20 square chips.

このようにチップサイズが大きくなって来ると支持体と
チップとの＊ｍ脹係数のミスマツチによりそのパッケー
ジのＬＳＩ支持体とチップ間の熱的厚みがＬＳＩ乃至超
ＬＳＩの特性に大きく現われ、その信頼性を低下せしめ
る不具合が浮び上シっ＼ある。また、チップサイズの長
寸化に伴って入出力用ビン数の増大も不可避でＩり、こ
れらのビン数に対応する数の貫通孔をＬＳＩ支持体に設
けんとする場合にはその加工精度の良いことが要求され
て来る。これに加えて、ＬＳＩ支持体が導電性でおる場
合に＃ｉ、上記貫通孔を含め走り−ド線を布線するＬＳ
Ｉ支持体部分を少なくと１絶縁しなければならな−が、
その絶縁処理の容易性が高いこともその製造工程上要求
される事項である。更には、チップサイズの長寸化は横
積的強度の増大を必要とするし、ｉ喪そのチップで発生
する熱の放熱性の良いことも当然に必要となって来る。As the chip size increases in this way, the thermal thickness between the LSI support of the package and the chip will greatly affect the characteristics of LSI or VLSI due to the mismatch in the *m expansion coefficient between the support and the chip, which will affect the reliability of the LSI or VLSI. There are a number of problems that have come to light that reduce performance. Furthermore, as the chip size becomes longer, the number of input/output bins will inevitably increase, and if the LSI support is to be provided with through-holes corresponding to the number of bins, the processing accuracy will have to be increased. Good things come in demand. In addition to this, if the LSI support is conductive, #i is used to wire the running wires including the through hole.
The support part must be insulated at least once.
High ease of insulation treatment is also required in the manufacturing process. Furthermore, increasing the size of the chip requires an increase in horizontal strength, and naturally it also becomes necessary to have good heat dissipation properties for the heat generated in the chip.

（３）　　従来技術と問題点 従来、ＬＳＩを収容するパッケージには、サーディツプ
形式のもの中プラグイン形式のもの等があるが、・その
ＬＳＩ支持体にはアル７ 板の材料例えばＳ（の線膨張係数２５Ｘ１０（ａｙｓ　
）の３倍強と大きい。そのため、熱的歪みをＬＳＩ乃至
超ＬＳ　ＩＫ惹起せしめその特性の劣化、ひいてはその
信頼性の低下を招来する原因となる。(3) Conventional technology and problems Conventionally, packages for accommodating LSIs include cer-dip type packages and plug-in type packages. Expansion coefficient 25X10 (ays
) is over three times larger. Therefore, thermal distortion is caused in the LSI or ultra-LSIK, resulting in deterioration of its characteristics and, ultimately, a decrease in its reliability.

（荀０発明の目的 本発明は上述のような従来パッケージの有する欠点ＫＩ
！みて創案されたもので、その目的は収容された集積回
路に熱的歪みが加−１わシに〈＼加工精度を高くし得る
外、良好な絶縁処理性を有する等の改良を図った集積回
路用パッケージを提供することに６る。(Xun0Object of the Invention The present invention aims to overcome the drawbacks of the conventional package as described above.
! Its purpose was to prevent thermal distortion from being applied to the integrated circuits housed in it. Our purpose is to provide circuit packages.

（旬１発明の構成 この目的は集積回路用パッケージの支持体をｐ−シリコ
ンカーバイトとし、この支持体に添着されそれＫて支持
される集積回路基板をＩ−シリコンカーバイトと熱的に
近似のものとすることによって達成される。(Structure of the First Invention) The purpose of this invention is to use p-silicon carbide as a support for an integrated circuit package, and make the integrated circuit board attached to and supported by this support thermally similar to I-silicon carbide. This is achieved by making it the

（−０発明の実施例 以下、添付図面を参照しながら本発明の詳細な説明する
。(-0 Embodiments of the Invention Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

第１図は本発明の１ｔｌｌの実施例を示す、１は支持体
で、これは−一シリコンカーバイトから成る。この支持
体には後述の如くして添着される集積回路（ＬＳＩ、超
ＬＳＩ等）の入出力端と電気的に接続されるビン２を挿
通するための貫通孔３が明けられ、この貫通孔と上記入
出力端に至る支持体部分とに少なくとも絶縁処理が施さ
れる。この絶縁処理は貫通孔３を明けられたβ−シリコ
ンカーバイトｌを酸化雰囲気中で酸化するととｋよって
達成される。その絶縁層を符号４で示す。FIG. 1 shows a 1tll embodiment of the invention, 1 is a support, which is made of -1 silicon carbide. This support is provided with a through hole 3 for inserting a vial 2 which is electrically connected to the input/output end of an integrated circuit (LSI, VLSI, etc.) to be attached as described later. and a support portion extending to the input/output end are at least insulated. This insulating treatment is achieved by oxidizing the β-silicon carbide with the through holes 3 in an oxidizing atmosphere. The insulating layer is designated by 4.

その支持体１上ＫＬＳＩ等を結合剤（金ペレット、ガラ
ス、樹脂等）で添着し、貫通孔３にビン２を挿通し、こ
のビンとＬＳＩ等の対応する入出力端とを電気的ＫＩＩ
続すると共に貫通孔３に充填剤５を充填して貫通孔３両
側間の気書性を得る。A KLSI etc. is attached on the support 1 with a binder (gold pellets, glass, resin, etc.), a bottle 2 is inserted into the through hole 3, and the corresponding input/output end of the LSI etc. is connected to the electrical KII.
At the same time, the through hole 3 is filled with a filler 5 to obtain air writing properties between both sides of the through hole 3.

上述のような各処理が施行された後−１支持体１の環状
端面６とキャップ７の対応する環状端面８との間にハン
〆ガラス又は樹脂等の結合剤を施与し、これら両者間を
結合して本発明のキャッププラグイン形式の集積回路用
パッケージが形成される。このパッケージ内に収容され
る上述の集積回路基板はβ−シリコンカーバイトと熱的
に近似する材料例えばシリコンである。こ＼で、両者の
線膨張係数を示せばシリコンが２　ｓ　ｘ　ｔ　Ｏ（ｅ
ｇｇ　　）でイ あり、ｐ−シリコンカーバイトは３９Ｘ１０（Ｃｇｓ）
である。After each of the above-mentioned treatments have been carried out, a binder such as glass or resin is applied between the annular end surface 6 of the support 1 and the corresponding annular end surface 8 of the cap 7, and a bonding agent such as glass or resin is applied between the two. A cap plug-in type integrated circuit package of the present invention is formed by combining the cap plug-in type integrated circuit package of the present invention. The above-mentioned integrated circuit board contained within this package is a material thermally similar to β-silicon carbide, such as silicon. Here, if we show the linear expansion coefficients of both, silicon is 2 s x t O(e
gg) and p-silicon carbide is 39X10 (Cgs)
It is.

従って、この本発明パッケージにおいては、支持体の熱
的歪みは集積回路基板に対しその集積回路機能を劣化乃
至衰失させるはどの有害な作用を及ぼさない、このこと
は特に１５〜２〇−角、更にはそれより長寸化された半
導体チップにおいてその有効性を発揮する。Therefore, in this inventive package, the thermal distortion of the support does not have any detrimental effect on the integrated circuit board to degrade or impair its integrated circuit function, which is particularly true for 15-20 Furthermore, it exhibits its effectiveness in semiconductor chips that are longer than that.

更には、−一シリコンカーバイトを酸化雰囲気中で酸化
させるだけでその表面層をＲ４ｏｔ化して絶縁層４を形
成するからその絶縁処理が極めて容易となる。また声−
シリコンカーバイトの熱伝導率がアルミナの熱伝導車の
５倍であるから放熱性に優れＬＳＩ等の温度上昇を少な
くしうるし、またその機械的強度感アルミナの２倍１ｉ
Ｔｏるから、長寸化されて要求される機械的強度の増大
にも応えられる。Furthermore, the insulating layer 4 is formed by changing the surface layer to R4ot by simply oxidizing -1 silicon carbide in an oxidizing atmosphere, making the insulating process extremely easy. Another voice
The thermal conductivity of silicon carbide is 5 times that of alumina, so it has excellent heat dissipation and can reduce the temperature rise of LSI, etc., and its mechanical strength is twice that of alumina.
Because of this, it can be made longer and meet the demands for increased mechanical strength.

第２図は本発明の第２の実施例を示す。この実施例はナ
ーデイツプ形式の集積回路用パッケージである。その構
造自体は従来と変わることなくその支持体１及びキャッ
プ７の材料としてｐ−シリコンカーバイトを用いた点に
相違がある。集積回路基板９の入出力端１０はリード線
１１．１２を経てビン１３．１４へ接続され、これらの
ビンの一端は支持体１の環状端面６とキャップ７の環状
端面８との間に施与されるガラス等の結合剤１５により
パッケージに強ＹＡＫ結合されている。また集積回路基
板９の下面はムｓ、Ｐｄ／ムｓ、Ｃｓ　　　ζ等の厚膜
焼付けにより一−シリコンカーバイト１の内面に固定さ
れて本発明のサーディツプ型の集積回路用パッケージが
構成されている。FIG. 2 shows a second embodiment of the invention. This embodiment is a nard dip type integrated circuit package. The structure itself is the same as before, but the difference is that p-silicon carbide is used as the material for the support 1 and the cap 7. The input and output ends 10 of the integrated circuit board 9 are connected via leads 11.12 to vials 13.14, one end of which is arranged between the annular end face 6 of the support 1 and the annular end face 8 of the cap 7. It is strongly YAK bonded to the package by a bonding agent 15 such as glass provided. Further, the lower surface of the integrated circuit board 9 is fixed to the inner surface of the -silicon carbide 1 by thick film baking of M, Pd/M, Cs, etc., thereby constructing the cerdip type integrated circuit package of the present invention. There is.

この構成よ抄得られる作用効果もその構造上の差違から
生ずる点を除いて同等である。The effects obtained from this configuration are also the same except for the differences in structure.

なお、本発明は他のパッケージ形式にも適用しうるもの
でありその詳細な説明を要しないと考えられるので、そ
の説明は省略する。It should be noted that the present invention can be applied to other package formats and does not require a detailed explanation thereof, so a detailed explanation thereof will be omitted.

（７）９発明の効果 以上の説明から明らかなように１本発明によれば次の効
果が得られる。(7) Effects of the 9th Invention As is clear from the above explanation, the following effects can be obtained according to the 1st invention.

■　チップが長寸化されても、熱的歪みを集積回路基板
に与えず、その集積回路機能を保全しその信頼性を維持
しうる。(2) Even if the chip becomes longer, thermal distortion will not be applied to the integrated circuit board, and the integrated circuit function and reliability can be maintained.

■　絶縁処理が非常に容易となる。■ Insulation treatment becomes very easy.

■　放熱性がよく集積回路の温度上昇に対する対策を緩
和しうる。■ It has good heat dissipation properties, making it possible to ease countermeasures against temperature rises in integrated circuits.

■　機械的強度が増大する等でるる。■ Mechanical strength increases, etc.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の第１の実施例を示す図、第２図は本発
明の第２０実施例を示す図である。 図中、１は支持体、９は集積回路基板、７はキャップ、
３は貫通孔、４は絶縁層、２はビン、５は充填剤、１１
，１２，１３．１４は入出力リード線、１５は結合剤で
ある。 特　許　出　願　人　　富士通株式金社第１図FIG. 1 shows a first embodiment of the invention, and FIG. 2 shows a twentieth embodiment of the invention. In the figure, 1 is a support, 9 is an integrated circuit board, 7 is a cap,
3 is a through hole, 4 is an insulating layer, 2 is a bottle, 5 is a filler, 11
, 12, 13, and 14 are input/output lead wires, and 15 is a bonding agent. Patent applicant Fujitsu Ltd. Gold Co., Ltd. Figure 1

Claims (1)

【特許請求の範囲】 （重）　　集積回路基板を添着して支える支持体にキャ
ップを気密的に結合して成る集積回路用パッケージにお
いて、夕立くとも上記支持体をβ−シリコンカーバイト
で形成し、上記集積回路基板を上記−一シリコンカーバ
イトと熱的に近似する材料で形成したことを特徴とする
集積回路用パッケージ。 （７）上記集積回路基板をシリコン半導体としたことを
特徴とする特許請求の範囲第１項記載の集積回路用パッ
ケージ。 （場　上記支持体に所ｌ！数の貫通孔を設け、少なくと
も該貫通孔を経て上記集積回路基板の入出力端に至る支
持体部を絶縁処理して入出力リード線を配置し、上記貫
通孔を気密的に封止して形成されて成ることを特徴とす
る特許請求の範囲第１項又は第２項記載の集積回路用パ
ッケージ。 （４）上鮎集積回路基板の入出力端の各々に対応する入
出力リード線を接続し、これら入出力リード線を上記支
持体と上記キャップとの結合部内で所定の間隔を隔て＼
配置され導出されて成ることを特徴とする特許請求の範
囲第１項又は第２項記載の集積回路用パッケージ。[Scope of Claims] (Major) An integrated circuit package comprising a cap hermetically bonded to a support that supports an integrated circuit board, wherein the support is made of β-silicon carbide. . An integrated circuit package, characterized in that the integrated circuit board is made of a material thermally similar to the -1 silicon carbide. (7) The package for an integrated circuit according to claim 1, wherein the integrated circuit substrate is a silicon semiconductor. (In this case, a number of through holes are provided in the support body, at least the support body portion that reaches the input/output ends of the integrated circuit board through the through holes is insulated, and input/output lead wires are arranged. The package for an integrated circuit according to claim 1 or 2, characterized in that the package is formed by airtightly sealing the hole. (4) Each of the input and output terminals of the Kamiayu integrated circuit board. Connect input/output lead wires corresponding to the above, and separate these input/output lead wires at a predetermined interval within the joint between the support body and the cap.
An integrated circuit package according to claim 1 or 2, characterized in that the integrated circuit package is arranged and led out.
JP21052881A 1981-12-26 1981-12-26 Package for integrated circuit Pending JPS58112347A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21052881A JPS58112347A (en) 1981-12-26 1981-12-26 Package for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21052881A JPS58112347A (en) 1981-12-26 1981-12-26 Package for integrated circuit

Publications (1)

Publication Number Publication Date
JPS58112347A true JPS58112347A (en) 1983-07-04

Family

ID=16590851

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21052881A Pending JPS58112347A (en) 1981-12-26 1981-12-26 Package for integrated circuit

Country Status (1)

Country Link
JP (1) JPS58112347A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55143042A (en) * 1979-04-25 1980-11-08 Hitachi Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55143042A (en) * 1979-04-25 1980-11-08 Hitachi Ltd Semiconductor device

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