JPS58112337A - Process of forming electrode of compound semiconductor device - Google Patents
Process of forming electrode of compound semiconductor deviceInfo
- Publication number
- JPS58112337A JPS58112337A JP21229581A JP21229581A JPS58112337A JP S58112337 A JPS58112337 A JP S58112337A JP 21229581 A JP21229581 A JP 21229581A JP 21229581 A JP21229581 A JP 21229581A JP S58112337 A JPS58112337 A JP S58112337A
- Authority
- JP
- Japan
- Prior art keywords
- compound semiconductor
- back side
- softening point
- semiconductor device
- gaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims abstract description 17
- 150000001875 compounds Chemical class 0.000 title claims abstract description 12
- 239000006023 eutectic alloy Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims abstract description 7
- 239000000203 mixture Substances 0.000 claims abstract description 6
- 229910000679 solder Inorganic materials 0.000 claims abstract description 5
- 230000005496 eutectics Effects 0.000 claims abstract description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 13
- 229910052737 gold Inorganic materials 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 238000009736 wetting Methods 0.000 abstract description 2
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 239000010931 gold Substances 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 229910017401 Au—Ge Inorganic materials 0.000 description 1
- -1 GaAs group compound Chemical class 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 235000021395 porridge Nutrition 0.000 description 1
- 229910002059 quaternary alloy Inorganic materials 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、例えばＧａＡｓのような化合物半導体装置の
裏面電極形成法に関するものである。以下、この種の半
導体装置の一例として、ＧａＡｓシａツ）キバリャ型電
界効果トランジスｆｉ （ＧａＡｓ ＭＥｓ ＦＥＴ）
の場合について説明する。 ＧａＡｓ ＭＥＳ ＦＥＴ
は、絶縁性ＧａＡｓ （ＣｒドープＧａＡｓ ）を基板
とし、この基板上にエピタキシャル成長したＧａλ＄動
作ｊ−上にゲート、ノース、ドレインｗｌ極を形成する
。トランジスタとしての機能は、すべてこれら動作層上
に形成された電極によってとシ行なわれ、その厚みはエ
ピタキシャル層も含めせいぜい１ミクロン以下である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a backside electrode of a compound semiconductor device such as GaAs. Hereinafter, as an example of this type of semiconductor device, a GaAs sheet) Kibalya type field effect transistor fi (GaAs MEs FET) will be described.
The case will be explained below. GaAs MES FET
In this method, an insulating GaAs (Cr-doped GaAs) substrate is used, and gate, north, and drain wl poles are formed on the Gaλ$ layer that is epitaxially grown on this substrate. All functions as a transistor are performed by electrodes formed on these active layers, and the thickness thereof including the epitaxial layer is at most 1 micron or less.
この様なプレナー型の半導体装置を所定のパッケージ又
はチップキャリヤ等に固定するには、通常半田を用いる
。Ｓｉ牛導体装置の場合には、パッケージのグイボンド
する面に金メッキ等を施し、λｕ−８ｉ共晶合金にて固
定する・ところが、ＧａＡｓ及びその他の化合物半導体
の場合は・ＡｕｏＧｅ 、 ＡｕｏＳｎ等の共晶合金を
用いるのが一般的である。そこで、素子の裏面はＣｒ／
Ａｕ等の多層金属膜を蒸着法等で形成し、上記共晶合金
のプリフォームを用いてグイボンドしていた。当然のこ
とながら、グイボンドが正しく行われるか否かは％素子
の信頼性を左右する重要なことである。Solder is usually used to fix such a planar semiconductor device to a predetermined package, chip carrier, or the like. In the case of a Si conductor device, the surface of the package to be bonded is plated with gold, etc., and fixed with λu-8i eutectic alloy. However, in the case of GaAs and other compound semiconductors, eutectic such as AuoGe or AuoSn is used. Generally, alloys are used. Therefore, the back side of the element is made of Cr/
A multilayer metal film such as Au is formed by a vapor deposition method or the like, and is bonded using a preform of the above-mentioned eutectic alloy. Naturally, whether or not Guibond is performed correctly is an important factor that determines the reliability of the device.
ところが従来は、素子裏面の最上表面に金薄膜を形成し
、半田との濡れを良くする様にしていたので、金蒸着工
程から実際にダイボンドする工程の間で汚染される場合
がしばしば有って、ダイボンドがうまく行かない場合が
あった。特に素子がペレット状になってから洗浄するこ
とは、非常に困難である。この発明はこの様な欠点を除
去したもので、プリフォームとの濡れ性の良好な電極形
成法を提供するものである。つまり、半導体基板の裏面
に、Ａｕ−Ｇｅ又はＡｕ−８ｎのような共晶半田と同一
組成の共晶合金を、その軟化点よシ低い温度に保ってＭ
着法又はスパッタ法で形成し、その後上記軟化点以上の
温度での熱処理をしないで裏面電極とすることを特徴と
するものである。その厚みハ０．１〜１．ＯＰが適蟲で
るる、博すざるとプリフォームとの濡れ性ががえって悪
くな）、１μ惰以上では効果ははとんど変わらず、かえ
って、ダイス分割時に裏面がつながる場合がある。とこ
ろで、ＧａＡｓなどの化合物半導体基板にＡｊ −Ｇｅ
山・ｓｎを生体とする金属膜を形成することは、オー
ミックコンタクトをとる方法として公知であるが、この
発明はオー２ツクコンタクトをとる九めに必要°とされ
る熱処理を含まない点に特徴がある。つまり、上記公知
技術は、良好なるオーミックコンタクトが形成できる最
適合金組成膜を形成して、３５０℃以上の高温でＧａＡ
ｓと合金化させるものである。こ−の場合、熱処理後の
金属膜面は、ボールアップ現象つｔｐてこほこになる。However, in the past, a thin gold film was formed on the top surface of the backside of the element to improve wetting with solder, which often resulted in contamination between the gold vapor deposition process and the actual die bonding process. , there were cases where Dibond did not work. In particular, it is extremely difficult to clean the elements after they have been turned into pellets. The present invention eliminates these drawbacks and provides a method for forming an electrode that has good wettability with a preform. In other words, a eutectic alloy having the same composition as the eutectic solder, such as Au-Ge or Au-8n, is placed on the back side of the semiconductor substrate and kept at a temperature lower than its softening point.
It is characterized in that it is formed by a deposition method or a sputtering method, and then is used as a back electrode without being subjected to heat treatment at a temperature above the softening point. Its thickness is 0.1~1. (If the OP is not suitable, the wettability with the preform will change and become bad).If it is over 1μ, the effect will not change at all, and the back sides may connect when dividing the dice. By the way, Aj -Ge is applied to a compound semiconductor substrate such as GaAs.
Forming a metal film with the mount/sn as a living body is a well-known method for making ohmic contact, but this invention is unique in that it does not include the heat treatment required to make ohmic contact. There is. In other words, the above-mentioned known technology forms a film with an optimum alloy composition that can form a good ohmic contact, and
It alloys with s. In this case, the surface of the metal film after the heat treatment becomes uneven due to a ball-up phenomenon.
この公知技術を裏面電極の形成に採用すると、次のよう
な不都合がある・（ａ）：３ｓｏ℃以上の熱処理では、
ＧａＡｓデペスはほとんど熱劣化する。これは通常、デ
ペイス製作前の工程でオーミックコンタクトを形成する
からでめるｅ （ｂ） ： ＧａＡｓと合金化したＡｕ
−Ｇｅ又はＡｕ−８ｎは複雑な四元合金となっておシ、
プリフォームとの濡れ性が悪い、これは、表面に伽が偏
析するためと考えられている。 （Ｃ） ：裏面かでと
ほこになっているので、平面にダイスを置いたとき傾く
、りまシ。When this known technique is adopted for forming the back electrode, there are the following disadvantages: (a): In heat treatment at 3so℃ or higher,
GaAs Depes is mostly thermally degraded. This is because ohmic contact is usually formed in the process before the device is manufactured.(b): Au alloyed with GaAs
-Ge or Au-8n forms a complex quaternary alloy;
The wettability with the preform is poor, and this is thought to be due to the segregation of porridge on the surface. (C): The back side is uneven, so when you place the die on a flat surface, it will tilt.
ダイスの表面観察時、ダイボンド時にハンドリングしに
くい。（ｄ）二合金組成がＡｕ−（３ｅ共晶合金または
Ａｕ−ａｎ共晶合金とは限らない、これらの理由で。Difficult to handle when observing the surface of the die or during die bonding. (d) The two-alloy composition is not necessarily Au-(3e eutectic alloy or Au-an eutectic alloy, for these reasons.
本発明はＡｕ−Ｇｅｔ九はＡｕ−８ｎの蒸着膜をそのま
＼、又は、その軟化点よシも低い温度で接着強度改善を
目的とする熱処理した膜を裏面電極とする点に特徴があ
る。The present invention is characterized in that the back electrode of Au-Get9 is a vapor-deposited film of Au-8n as it is, or a film heat-treated at a temperature lower than its softening point for the purpose of improving adhesive strength. .
このようにして形成した裏面電極は、従来のような金蒸
着膜であればその表面が汚染された場合にプリフォーム
との濡れが悪かったのにくらぺ。The back electrode formed in this way has poor wettability with the preform when the surface becomes contaminated, compared to the conventional gold vapor-deposited film.
フリフオームと同一組成の蒸着膜であるので、一旦とけ
あって、プリフォームとよくなじむという効果もめる。Since the deposited film has the same composition as the freeform, it has the effect of melting once and blending well with the preform.
したがって、表面が少しぐらい汚れていても、影響はほ
とんど無い。Therefore, even if the surface is slightly dirty, it has almost no effect.
以上、ＧａＡｓ ＭＢ２ ＦＥＴの裏面電極形成にうい
モ説明してきたが、半導体装置として上記に限定される
ものではなく、この発明はＧａＡｓ以外の他の厘−マ族
化合物半導体の裏面電極形成に適用できる。Although the formation of a backside electrode of a GaAs MB2 FET has been described above, the semiconductor device is not limited to the above, and the present invention can be applied to the formation of a backside electrode of a GaAs group compound semiconductor other than GaAs. .
代理人 葛野信−
手続補正書（１！Ｉ発］
特許庁長官殿
１、事件の表示 特願昭ｓｓ−ｓ５５−５ｔ号２
、発明の名称
化合物半導体装置の電極形成法
３、補正をする者
６、補正の対象
明細書の発明の詳細な説明の欄
６、補正の内容
（１）明細書第４頁第１１行目に「デベス」とあるのを
「デバイス」と訂正する。Agent Makoto Kuzuno - Procedural amendment (issued by 1!I) Commissioner of the Japan Patent Office 1, Indication of case Patent application Sho SS-S55-5T No. 2
, Title of the invention: Method for forming electrodes for compound semiconductor devices 3, Person making the amendment 6, Detailed description of the invention in the specification subject to amendment 6, Contents of the amendment (1) On page 4, line 11 of the specification Correct the word "device" to "device."
（２）明細書第４頁第１２行目に−「デバイス」とある
のを「デバイス」と訂正する。(2) On page 4, line 12 of the specification, the word "device" is corrected to "device."
以上that's all
Claims (3)
共晶半田と同一組成の共晶合金膜を、少なくとも上記共
晶合金膜の軟化点以上の温度で熱処理することなく化合
物半導体基板に形成して、主起固定用の電極を形成する
仲とを特徴とする化合物半導体装置の電極形成法。(1) A eutectic alloy film having the same composition as the eutectic solder used to fix a compound semiconductor device to a support is formed on a compound semiconductor substrate without heat treatment at a temperature at least higher than the softening point of the eutectic alloy film. 1. A method for forming an electrode for a compound semiconductor device, the method comprising: forming an electrode for active fixation;
膜は緬・ＧｅまたはＡｕ−８ｎ共晶合金からなる特許請
求の範囲第１項記載の化合物半導体装置の電極形成法・(2) A method for forming an electrode in a compound semiconductor device according to claim 1, wherein the compound semiconductor substrate is made of GaAa, and the eutectic alloy film is made of Burmese-Ge or Au-8n eutectic alloy.
許請求の範囲第１項記載の化合物半導体装置の電極形成
法。(3) The method for forming an electrode for a compound semiconductor device according to claim 1, wherein the eutectic alloy film has a thickness of 0.1 to 1.0 PK.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21229581A JPS58112337A (en) | 1981-12-25 | 1981-12-25 | Process of forming electrode of compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21229581A JPS58112337A (en) | 1981-12-25 | 1981-12-25 | Process of forming electrode of compound semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58112337A true JPS58112337A (en) | 1983-07-04 |
| JPH0221135B2 JPH0221135B2 (en) | 1990-05-11 |
Family
ID=16620211
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21229581A Granted JPS58112337A (en) | 1981-12-25 | 1981-12-25 | Process of forming electrode of compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58112337A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5011182A (en) * | 1973-05-28 | 1975-02-05 | ||
| JPS5530834A (en) * | 1978-08-25 | 1980-03-04 | Nec Corp | Method of forming ohmic contact in semiconductor pellet |
-
1981
- 1981-12-25 JP JP21229581A patent/JPS58112337A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5011182A (en) * | 1973-05-28 | 1975-02-05 | ||
| JPS5530834A (en) * | 1978-08-25 | 1980-03-04 | Nec Corp | Method of forming ohmic contact in semiconductor pellet |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0221135B2 (en) | 1990-05-11 |
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