JPS6142147A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6142147A JPS6142147A JP16255284A JP16255284A JPS6142147A JP S6142147 A JPS6142147 A JP S6142147A JP 16255284 A JP16255284 A JP 16255284A JP 16255284 A JP16255284 A JP 16255284A JP S6142147 A JPS6142147 A JP S6142147A
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05073—Single internal layer
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H01L2924/01022—Titanium [Ti]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は、半導体基体としてガリウムヒ素（以下、Ｇａ
Ａｓという。）を用いた半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Industrial application field The present invention uses gallium arsenide (hereinafter referred to as Ga) as a semiconductor substrate.
It is called As. ).
一ト電界効果トランジスタ（以下、ＧａＡｓ−ＭＥＳＦ
ＥＴという。）は、低雑音、高利得など優れた特性をも
つマイクロ波帯増幅素子として実用化されている。GaAs-MESF
It's called ET. ) has been put into practical use as a microwave band amplification element with excellent characteristics such as low noise and high gain.
ＧａＡｓ−ＭＥＳＦＥＴは第４図および第５図に示すよ
うに、Ｃｒドープまたはアンドープの半絶縁体となった
基板（ロ）上にイオン注入および活性化アニールにより
ル型（ドナー濃度約１０ｃＩｒＬ）の活性層（２）を設
けたＧａＡｓ半導体基体（１）を備え、活性層（６）上
にソースおよびドレイン電極とゲート電極をリストオフ
法により形成している。すなわち、ソース電極０とドレ
イン電極α４を活性層（２）にオーミック接触して設け
ると共に、ソース電極□□□とドレイン電極（ロ）との
間にゲート電極（ト）（ト）を活性層（イ）にショット
キ接触して設けている。As shown in Figs. 4 and 5, GaAs-MESFETs are made with Cr-type (donor concentration approximately 10 cIrL) activation by ion implantation and activation annealing on a Cr-doped or undoped semi-insulating substrate (b). A GaAs semiconductor substrate (1) provided with a layer (2) is provided, and source and drain electrodes and a gate electrode are formed on an active layer (6) by a list-off method. That is, the source electrode 0 and the drain electrode α4 are provided in ohmic contact with the active layer (2), and the gate electrode (T) (T) is provided between the source electrode □□□ and the drain electrode (B) in the active layer (2). A) is provided in Schottky contact.
ところで、ＧａＡｓ基体（１）とオーミック接触をとる
方法としては、基体（１）表面にオーミック接触形成金
属な被着した後、適当な合金化熱処理工程により前記金
属と基体との間に、合金化反応を進行させ、オーミック
接触をとる方法が一般的である。現在用いられているオ
ーミック接触形成金属のうち、最もよく使用されている
のはＡｕ（金）を主成分とする合金、例えばＡｕＧｅ（
・金・ゲルマニウム）合金である。また、特開昭５９−
２８３７６号公報に示すように、オーミック電極の接触
抵抗を減らすためにＡ ｕ Ｇ ｅ Ｇ ａ合金を用い
た半導体装置がある。By the way, as a method for making ohmic contact with the GaAs substrate (1), after depositing an ohmic contact forming metal on the surface of the substrate (1), alloying is performed between the metal and the substrate by an appropriate alloying heat treatment process. A common method is to allow the reaction to proceed and establish ohmic contact. Among the currently used ohmic contact forming metals, the most commonly used are alloys whose main component is Au (gold), such as AuGe (
・Gold/germanium) alloy. Also, JP-A-59-
As shown in Japanese Patent No. 28376, there is a semiconductor device using an AuGeGa alloy to reduce the contact resistance of an ohmic electrode.
第６図は従来のソース電極（２）およびドレイン電極（
ロ）を模式的断面図をもって示すものである。ＧａＡｓ
基体（１）の表面に形成された電極には、外部引出しリ
ード等の金属体と電気的に接続するためＫＡｕ線よりな
るリード線（財）がボンディングされる。したがって、
その電極表面にはボンディング性向上のためにＡｕ層曽
が設けられている。また、ＡｕＧｅ層（２）と電極表面
のＡｕ層（ホ）との間ＫＡｕ層曽０密着性を良好にする
ためにＴｉ（チタン）層＠Ｎｉにッケル）０翰を介在さ
せている。また第７図の様にＡｕＧｅ層（財）、Ｎｉ層
四で合金化し、その上にポンディングパッドとしての第
２電極としてＴｉ層翰、Ａｕ層（イ）を形成する場合も
ある。Figure 6 shows the conventional source electrode (2) and drain electrode (
b) is shown with a schematic cross-sectional view. GaAs
Lead wires made of KAu wires are bonded to the electrodes formed on the surface of the base (1) for electrical connection to metal bodies such as external leads. therefore,
An Au layer is provided on the surface of the electrode to improve bonding properties. Further, in order to improve the adhesion of the KAu layer between the AuGe layer (2) and the Au layer (e) on the electrode surface, a Ti (titanium) layer @Ni is interposed. Alternatively, as shown in FIG. 7, an AuGe layer and a Ni layer may be alloyed, and a Ti layer and an Au layer may be formed thereon as a second electrode as a bonding pad.
（ハ）発明が解決しようと５る問題点
しかしながら、第６図で示した電極構造では、基体（１
）とＡｕＧｅ層（ハ）との合金層の破壊強度が小さいた
めボンディングの際、電極部分の基体（１）のクラック
による電極ハガレや熱処理後の表面Ａｕ層員の変質に伴
なうボンディング付着性の劣化があった。また第７図の
構造でも第１電極のＮｉ層翰と第２電極のＴｉ層（イ）
の接着強度が小さいため、ボンディングの際第２電極が
はがれる問題があった。(c) Problems that the invention seeks to solve However, in the electrode structure shown in FIG.
) and the AuGe layer (c) have a low fracture strength, during bonding, the electrode peels off due to cracks in the base (1) of the electrode part, and bonding adhesion due to deterioration of the surface Au layer after heat treatment. There was deterioration. Also, in the structure shown in Fig. 7, the Ni layer of the first electrode and the Ti layer of the second electrode (a)
Because of the low adhesive strength, there was a problem that the second electrode would peel off during bonding.
に）問題点を解決するための手段
本発明は上述した問題点を解消するためになされたもの
にして、ガリウムヒ素半導体基体と、この半導体基体の
所定領域に接触させた電極とを具備する半導体装置にお
いて、前記電極上に、チタンに金を積層した第２電極層
を配設すると共に、この第２電極層を半導体基体まで延
在して半導体基体と接続させ、半導体基体上に位置する
第２電極層上にリード線をボンディングしたことを特徴
とする。B) Means for Solving the Problems The present invention has been made to solve the above-mentioned problems, and provides a semiconductor comprising a gallium arsenide semiconductor substrate and an electrode in contact with a predetermined region of the semiconductor substrate. In the device, a second electrode layer made of gold laminated on titanium is disposed on the electrode, the second electrode layer is extended to the semiconductor substrate and connected to the semiconductor substrate, and a second electrode layer located on the semiconductor substrate is provided. A feature is that lead wires are bonded onto two electrode layers.
に）作用
本発明によれば、Ｇ ａ Ａ ｓ基体上に密着性の良好
なチタンが接続し、その位置でリード線をボンディング
するので、電極がボンディング作業の際にはがれるおそ
れはない。B) Function According to the present invention, since titanium with good adhesion is connected to the GaAs substrate and the lead wire is bonded at that position, there is no fear that the electrode will come off during the bonding operation.
（へ）実施例
以下本発明の一実施例を第１図ないし第３図に従い説明
する。第１図は本発明によるＧａＡｓ−ＭＥＳＦＥＴの
上面図、第２図は第１図の■−■線断面図、第３図は本
発明の電極構造を説明するための模式的断面図である。(f) Example An example of the present invention will be described below with reference to FIGS. 1 to 3. FIG. 1 is a top view of a GaAs-MESFET according to the present invention, FIG. 2 is a cross-sectional view taken along the line ■--■ in FIG. 1, and FIG. 3 is a schematic cross-sectional view for explaining the electrode structure of the present invention.
本実施例のＧａＡｓ−ＭＥＳＦＥＴは、第１図および第
２図に示すように、ソース電極（至）とドレイン電極へ
４との間に、第１ゲート電極（至）および第２ゲート電
極（ト）からなる２本のゲート電極を設けたいわゆるデ
エアルゲート構造となっている。第１図において、各電
極のボンディング領域は鎖線で示している。As shown in FIGS. 1 and 2, the GaAs-MESFET of this example has a first gate electrode (to) and a second gate electrode (to) between the source electrode (to) and the drain electrode ) has a so-called deaial gate structure in which two gate electrodes are provided. In FIG. 1, the bonding area of each electrode is indicated by a chain line.
ＧａＡａ−ＭＥＳＦＥＴは、第２図に示すように、Ｃｒ
ドープまたはアンドープによって半絶縁体となった基板
（ロ）上に、イオン注入および活性化アニールによっｔ
形成した１型（ドナー濃度的１０”ｍ−８）活性層（イ
）上に各電極を配している。GaAa-MESFET is made of Cr as shown in FIG.
On the substrate (b), which has become a semi-insulator by doping or undoping, t is formed by ion implantation and activation annealing.
Each electrode is arranged on the formed type 1 (10''m-8 in terms of donor concentration) active layer (a).
なお基板αｐ、ル型活性層（６）を含めてＧａＡｓ基体
（１）という。Note that the substrate αp and the square active layer (6) are collectively referred to as a GaAs substrate (1).
九型活性層（２）表面の中央には１μｍ〜１．５μｍの
幅の２本のゲート電極がショットキ接触して配置される
。２本のゲート電極は、それぞれ、第１ゲート電極（至
）および第２ゲート電極（至）を構成する。Two gate electrodes each having a width of 1 μm to 1.5 μm are arranged in Schottky contact at the center of the surface of the type 9 active layer (2). The two gate electrodes constitute a first gate electrode (to) and a second gate electrode (to), respectively.
また、２本のゲート電極をはさんで、ソース電極＠とド
レイン電極α荀がオーミック接触して配置される。ここ
で、ＧａＡｓ基体（１）とオーミック接触するソース電
極（２）およびドレイン電極Ｑ４は第３図に示すように
最下層に厚さｌ１００ＡのＡｕ−Ｇｅ層（ハ）、中間層
に厚さ４００ＡのＮｉ＃（ホ）厚さ１０００ＡのＴｉ層
（財）と最上層の厚さ３０００ＡのＡｕ層曽を蒸着によ
って積層して構成されている。Further, the source electrode @ and the drain electrode α are arranged in ohmic contact with the two gate electrodes in between. Here, as shown in FIG. 3, the source electrode (2) and the drain electrode Q4 which are in ohmic contact with the GaAs substrate (1) have an Au-Ge layer (c) with a thickness of 1100A as the bottom layer and a layer with a thickness of 400A as the intermediate layer. It is constructed by laminating a Ti layer (goods) with a thickness of 1000 Å and an Au layer with a thickness of 3000 Å as the top layer by vapor deposition.
そして、本発明はこのように構成したソース電極（ｌａ
およびドレイン電極α４上に、厚さ１００ＯＡのＴｉ［
ｆｉと厚さ３０００ＡのＡｕ１ｉＣ１１）を積層した第
２電極層（３）を配設し、そして、第２電極層（３）を
ＧａＡｓ基体（１）まで延在させ、ＧａＡｓ基体（１）
と密着性の高いＴｉ（Ｉｎを接触させる。The present invention also provides a source electrode (la
And on the drain electrode α4, a Ti[
A second electrode layer (3) in which fi and Au1iC11) having a thickness of 3000 A are laminated is provided, and the second electrode layer (3) is extended to the GaAs substrate (1).
and Ti(In), which has high adhesion, are brought into contact with each other.
また、第１および第２ゲート電極ａＪ１９ＱｌＳは最下
層に厚さ１５００ＡのＴｉ層と中間層に厚さ５００Ａの
ｐｔ層と最上層に厚さ３０００ＡのＡｕ層を蒸着によっ
て積層して構成される。本実施例では、第１および第２
ゲート電極（至）（２）上にも前述したように第２電極
層（３）が配設されている。The first and second gate electrodes aJ19QlS are formed by stacking a Ti layer with a thickness of 1500 Å as the bottom layer, a PT layer with a thickness of 500 Å as the intermediate layer, and an Au layer with a thickness of 3000 Å as the top layer by evaporation. In this example, the first and second
As described above, the second electrode layer (3) is also provided on the gate electrode (2).
そして、ゲート形成前に合金化熱処理を行うことによっ
て、ノース電極（２）およびドレイン電極α４はＧａＡ
ｓ基体（１） Ｋオーミック接触すると共に、第１およ
び第２ゲート電極（至）（ト）はＧ ａ Ａ ｓ基体（
１）Ｋショットキ接触する。また、第２電極層（３）も
Ｇａ Ａ ｓ基体（１）にショットキ接触するが、第２
電極層（３）がショットキ接触するＧａＡｓ基体（１）
の箇所は半絶縁体で構成しているので、Ｇ ａ Ａ ｓ
−ＭＥＳＦＥＴの動作に対しては影響を及ぼさないよ
うになっている。By performing alloying heat treatment before gate formation, the north electrode (2) and drain electrode α4 are made of GaA.
s substrate (1) While making K-ohmic contact, the first and second gate electrodes (to) (g) are connected to the Ga A s substrate (
1) K Schottky contact. Further, the second electrode layer (3) also makes Schottky contact with the GaAs substrate (1), but the second electrode layer (3)
GaAs substrate (1) with Schottky contact with electrode layer (3)
Since the part is made of semi-insulator, G a A s
- The operation of the MESFET is not affected.
尚、電極形成領域以外の活性層（ロ）表面および半絶縁
体基体（ロ）上には絶縁膜が設けられていると共に、第
２電極層（ａ）ｃｒｙ、、−ｙンデ゛くング領域以外の
ＧａＡｓ−ＭＥＳＦＥＴ表面はパッシベーション膜が設
けられている。Note that an insulating film is provided on the surface of the active layer (b) other than the electrode formation region and on the semi-insulating substrate (b), and the second electrode layer (a) cry, -y indexing A passivation film is provided on the surface of the GaAs-MESFET other than the area.
而して、リード線αηの各電極に対するボンディングは
、ＧａＡｓ基板（１）上に位置する第２電極層（３）上
に行われ、リード線αηが第２電極層（３）上に接続さ
れ、電極の取り出しが行なわれる。すなわち、接着強度
の大きい、第２電極層（３）上でボンディングするので
、第２電極層（３）がはがれるおそれはない。また、た
とえ、第２電極層（３）とＧａＡｓ基体（１）との間に
、ボンディングの際剥離が生じたとしても、各電極と第
２電極′層（３）は密着しているので、断線なども生じ
ない。Bonding of the lead wire αη to each electrode is performed on the second electrode layer (3) located on the GaAs substrate (1), and the lead wire αη is connected to the second electrode layer (3). , the electrode is taken out. That is, since bonding is performed on the second electrode layer (3), which has a high adhesive strength, there is no fear that the second electrode layer (3) will peel off. Furthermore, even if peeling occurs between the second electrode layer (3) and the GaAs substrate (1) during bonding, each electrode and the second electrode' layer (3) are in close contact with each other. No wire breakage occurs.
尚、本実施例では、ソース電極（至）およびドレイン電
極α尋をＡｕ Ｇｅ層（至）、Ｎｉ層（２）、Ｔ１層
（イ）ＡｕｌＨ！Ｉ）で構成しているが、Ａｕ−Ｇｅ層
（２）などのオーミック接触形成金属を単層で構成し、
その上に第２電極層（３）を配設して構成することもで
きる。また第１および第２ゲート電極（至）（ト）もＴ
ｉ層などのショットキ接触形成金属を単層で構成し、そ
の上に第２電極層（３）を配設して構成することもでき
る。In this example, the source electrode (to) and the drain electrode are formed by Au Ge layer (to), Ni layer (2), and T1 layer (A). I), but it is composed of a single layer of ohmic contact forming metal such as Au-Ge layer (2),
It is also possible to arrange a second electrode layer (3) thereon. Also, the first and second gate electrodes (to) (g) are also T
It is also possible to configure the Schottky contact forming metal such as the i-layer to be a single layer, and to arrange the second electrode layer (3) thereon.
（ト）発明の詳細
な説明したようＫ、本発明によれば、ボンディング作業
の際に、電極が剥離することもなくなり、信頼性の高い
半導体装置を提供することができる。(G) Detailed Description of the Invention According to the present invention, electrodes do not peel off during bonding operations, and a highly reliable semiconductor device can be provided.
＠１図ないし第３図は本発明の一実施例を示し、第１図
は本発明によるＧａＡｓ−ＭＥＳＦＥＴの上面図、第２
図は第１図の■−■線断面図、第３図は電極構造を示す
模式断面図である。第４図ないし第７図は従来例を示し
、第４図はＧａＡｓ−ＭＥＳＦＥＴ（７）上面図、第５
図ハ第４図１７）Ｖ−Ｖ線断面図、第６図および第７図
は電極構造を示す模式断面図である。
（１）・・・ＧａＡｓ基体、 α岨・・基体、 （２）
・・・活性層、Ｑ３・・・ソース電極、 αか・・ドレ
イン電極、ｑｏ、（２）・・・ゲート電極、 （３）・
・・第２電極層。
第１図
第２図
−一、−ノ
第４図
第７図@Figures 1 to 3 show one embodiment of the present invention, and Figure 1 is a top view of the GaAs-MESFET according to the present invention, and Figure 2 is a top view of the GaAs-MESFET according to the present invention.
The figure is a cross-sectional view taken along the line ■--■ in FIG. 1, and FIG. 3 is a schematic cross-sectional view showing the electrode structure. 4 to 7 show conventional examples, FIG. 4 is a top view of GaAs-MESFET (7), and FIG.
17) A sectional view taken along the line V-V, and FIGS. 6 and 7 are schematic sectional views showing the electrode structure. (1)...GaAs substrate, α...substrate, (2)
...active layer, Q3...source electrode, α...drain electrode, qo, (2)...gate electrode, (3)...
...Second electrode layer. Figure 1 Figure 2-1,--Figure 4 Figure 7
Claims (1)
定領域に接触させた電極とを具備する半導体装置におい
て、前記電極上に、チタンに金を積層した第２電極層を
配設すると共に、この第２電極層を半導体基体まで延在
して半導体基体と接続させ、半導体基体上に位置する第
２電極層上にリード線をボンディングしたことを特徴と
する半導体装置。(1) In a semiconductor device comprising a gallium arsenide semiconductor substrate and an electrode in contact with a predetermined region of the semiconductor substrate, a second electrode layer made of gold laminated on titanium is disposed on the electrode; A semiconductor device characterized in that a second electrode layer extends to a semiconductor substrate and is connected to the semiconductor substrate, and a lead wire is bonded onto the second electrode layer located on the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59162552A JPH065688B2 (en) | 1984-08-01 | 1984-08-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59162552A JPH065688B2 (en) | 1984-08-01 | 1984-08-01 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6142147A true JPS6142147A (en) | 1986-02-28 |
| JPH065688B2 JPH065688B2 (en) | 1994-01-19 |
Family
ID=15756758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59162552A Expired - Lifetime JPH065688B2 (en) | 1984-08-01 | 1984-08-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH065688B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63106902U (en) * | 1986-12-29 | 1988-07-11 | ||
| JPH03500076A (en) * | 1987-06-10 | 1991-01-10 | ハイルマイア ウント バインライン ファブリク フュル オエル ハイドロリク ゲーエムベーハー ウント コンパニー，カーゲー | threaded type valve housing |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56142678A (en) * | 1980-04-07 | 1981-11-07 | Nec Corp | Field effect transistor |
-
1984
- 1984-08-01 JP JP59162552A patent/JPH065688B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56142678A (en) * | 1980-04-07 | 1981-11-07 | Nec Corp | Field effect transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63106902U (en) * | 1986-12-29 | 1988-07-11 | ||
| JPH03500076A (en) * | 1987-06-10 | 1991-01-10 | ハイルマイア ウント バインライン ファブリク フュル オエル ハイドロリク ゲーエムベーハー ウント コンパニー，カーゲー | threaded type valve housing |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH065688B2 (en) | 1994-01-19 |
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