JPS58111764A - Testing method of printed board - Google Patents

Testing method of printed board

Info

Publication number
JPS58111764A
JPS58111764A JP56215636A JP21563681A JPS58111764A JP S58111764 A JPS58111764 A JP S58111764A JP 56215636 A JP56215636 A JP 56215636A JP 21563681 A JP21563681 A JP 21563681A JP S58111764 A JPS58111764 A JP S58111764A
Authority
JP
Japan
Prior art keywords
terminal
hold
signal
tester
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56215636A
Other languages
Japanese (ja)
Inventor
Yasuyuki Takahashi
泰行 高橋
Yoshihito Oota
太田 意人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP56215636A priority Critical patent/JPS58111764A/en
Publication of JPS58111764A publication Critical patent/JPS58111764A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2806Apparatus therefor, e.g. test stations, drivers, analysers, conveyors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Supply And Installment Of Electrical Components (AREA)

Abstract

PURPOSE:To enable debugging with an IC kept packaged by having a test signal inputted into the IC after a hold signal is inputted into a hole terminal of the IC to make the output terminal thereof electrically inactivated with a high impedance. CONSTITUTION:An IC 11 with a hold terminal is packaged on a printed board 10 and has a plurality of terminals 12 comprising a normal input/output terminal, a power source terminal and the like and a testing hold terminal 13. A test signal from a tester 14 and a hold signal are fetched through an IC connection probe 15. In the debugging of the board 10, the power source of the board 10 is turned off and a probe 15 is set to terminals 12 and 13 to input the hold signal into the terminal 13. Then, when the power source is closed to the board 10, all the output terminals of the IC are made inactivated electrically with a high impedance. Under such a condition, when a test signal of the tester 14 is inputted into the terminal 12, debugging can be done without causing competition between the test signal and output signals of the IC 11.

Description

【発明の詳細な説明】 本発明は、集積回路(以下、ICという)を実装したプ
リント基板におけるハードウェア上のデバッグを行なう
際にICを実装したままでデバッグを行なえるプリント
基板の試験方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a printed circuit board testing method that allows hardware debugging of a printed circuit board on which an integrated circuit (hereinafter referred to as an IC) is mounted to perform debugging with the IC mounted thereon. It is something.

従来、プリント基板のデバッグを行なうには、第1図に
示すように、プリント基板1上の試験信号を入力とする
工C2の取付位置に工Cソケット3を使用し、試験に際
しICソケット3から工C2をはずし、この工Cソケッ
ト3に試験用プローブ4を挿入して各々の試験信号を外
部試験装置(以下、テスタという)5からプローブ4を
介して供給することによシ、デバッグを行なう方法がと
られていた。
Conventionally, in order to debug a printed circuit board, as shown in FIG. Debugging is performed by removing the tester C2, inserting a test probe 4 into the tester C socket 3, and supplying each test signal from an external test device (hereinafter referred to as a tester) 5 via the probe 4. A method was taken.

ところで、現在、量産品の組立作業では、IC等の部品
については自動挿入機が採用され、極めて高い能率を上
げているが、ICソケットについては自動挿入機の使用
ができないはかシか、自動はんだ何種にプリント基板を
流す際フラックスがICソケットのピンに浸入し、接触
不良を発生させる問題がある。
By the way, currently, in the assembly work of mass-produced products, automatic insertion machines are used for components such as ICs, and are extremely efficient, but automatic insertion machines cannot be used for IC sockets. When pouring solder onto a printed circuit board, the flux may seep into the pins of the IC socket, causing poor contact.

そのために、自動はんだ何種、洗浄を経た後、手作業に
おいて後付は作業を行ない、さらに手作業によるはんだ
付けの後、プリント基板のはんだ何面に付着したフラッ
クスの洗浄を行なう作業工程が必要となり、プリント基
板内に唯一つの工Cソケットが存在しても、それに伴な
う工数増加は無視できないものになっている。
To do this, it is necessary to perform several types of automatic soldering and cleaning, then manually perform retrofit work, and then after manual soldering, a work process is required in which the flux adhering to the solder surface of the printed circuit board is cleaned. Therefore, even if there is only one C-socket in the printed circuit board, the increase in man-hours associated with it cannot be ignored.

このように、プリント基板におけるノ・−ドウエア上の
デバッグをテスタで行なう場合、基板上のICソケット
を介してテスタからの試験信号を基板に入力するように
すると、ICソケットの実装による工数の増加およびフ
ラックス等による接触不良が起ることなどから、ICソ
ケットを使用せずICを直かにプリント基板に実装した
ままでデバッグが行なえる試験方法が要望されていた。
In this way, when using a tester to debug the hardware on a printed circuit board, if the test signal from the tester is input to the board via the IC socket on the board, the number of man-hours required for mounting the IC socket will increase. Also, there is a need for a test method that allows debugging without using an IC socket and with the IC mounted directly on a printed circuit board, since poor contact may occur due to flux or the like.

本発明はこのような点に鑑みてなされたもので、その目
的は、テスタからの試験信号を、ICソケットを介して
入力せずプリント基板実装済みのICの端子に直接入力
してデバッグを行なえるプリント基板の試験方法を提供
することにある。
The present invention has been made in view of these points, and its purpose is to enable debugging by directly inputting test signals from a tester to the terminals of an IC mounted on a printed circuit board, without inputting them through an IC socket. The purpose of this invention is to provide a method for testing printed circuit boards.

このような目的を達成するため、本発明は、テスタから
の試験信号を入力とするプリント基板上の実装済みのI
Cにホールド端子を設けておき、テスタからの試験信号
に先立ってホールド信号を前記ホールド端子に入力して
当該ICの出力端子をハイインピーダンスにして電気的
に非活性化した後、試験信号を前記ICに直接入力する
ようにしたものである。
In order to achieve such an object, the present invention provides an integrated circuit board mounted on a printed circuit board that receives test signals from a tester.
A hold terminal is provided at C, and a hold signal is inputted to the hold terminal prior to the test signal from the tester to make the output terminal of the IC high impedance and electrically inactivated, and then the test signal is input to the hold terminal. It is designed to be input directly to the IC.

以下、本発明の一実施例を図につき説明する。An embodiment of the present invention will be described below with reference to the drawings.

第2図は本発明によるプリント基板の試験方法を示す説
明図である。同図において、10は各種のIC(図示せ
ず)と後述するテスタからの信号を入力とするホールド
端子付き工C11が実装された従来と同様のプリント基
板であシ、前記ホールド端子付き工C11は、通常の入
出力端子、電源端子々とからガる複数の端子12と試験
用のホールド端子13とを有し、とのホールド端子13
に後述するテスタからのホールド信号が入力されること
によシ、複数の端子12のうちすべての出力端子をハイ
インピーダンスにするものとなっている。14は前記プ
リント基板10におけるノ・−ドウエア上のデバッグの
ために必要なる各種の試験信号およびホールド信号を出
力するテスタであり、このテスタ14からの試験信号お
よびホールド信号などの信号は工C接続用グローブ15
を通じて取り出される。そして、試験に際しIC接続用
プローブ15をホールド端子付き工C11の各端子12
およびホールド端子13に接続することにより、ホール
ド端子13には上記ホールド信号がテスタ14のホール
ド信号出力端子16から前記プローブ15を介して常時
入力され、各端子12には同じく各試験信号が試験信号
出力端子17から入力されるものとなっている。なお、
15aはICeC相続ローブ15のケーブルである。
FIG. 2 is an explanatory diagram showing a printed circuit board testing method according to the present invention. In the same figure, reference numeral 10 denotes a printed circuit board similar to the conventional one, on which various ICs (not shown) and a hold terminal C11 which inputs signals from a tester to be described later are mounted. has a plurality of terminals 12 connected to normal input/output terminals, a power supply terminal, etc., and a hold terminal 13 for testing.
By inputting a hold signal from a tester, which will be described later, all the output terminals among the plurality of terminals 12 are set to high impedance. 14 is a tester that outputs various test signals and hold signals necessary for debugging the hardware on the printed circuit board 10, and signals such as test signals and hold signals from this tester 14 are connected to the circuit C. glove 15
taken out through. Then, during the test, the IC connection probe 15 is held at each terminal 12 of the terminal C11.
By connecting the hold terminal 13 to the hold terminal 13, the hold signal is constantly inputted to the hold terminal 13 from the hold signal output terminal 16 of the tester 14 via the probe 15, and each test signal is also input to each terminal 12. The signal is input from the output terminal 17. In addition,
15a is a cable of the ICeC inheritance lobe 15.

しかして、プリント基板のデバッグに際し、プリント基
板10の電源を切ってからテスタ14からのホールド信
号が出力されているIC接続用プローブ15を、ホール
ド端子付き工C11の各端子12およびホールド端子1
3に正しくセットし、このホールド信号を前記ホールド
端子13に入力する。そして、プリント基板10の電源
を投入すると、前記工C11は、テスタ14からのホー
ルド信号が入力されておシ、その出力端子のすべてがハ
イインピーダンスとなって電気的に非活性化される。こ
の状態でテスタ14からプローブ15を介して試験信号
をホールド端子付きIC1iの各端子12に入力すると
、この工C11の各端子にはテスタ14からの試験信号
だけが入力されることになり、したがって、テスタ14
の試験信号とホールド端子付きICi lの出力信号が
競合してプリント基板の回路の暴走や回路素子の破壊を
引き起すおそれはなくなる。
Therefore, when debugging a printed circuit board, after turning off the power to the printed circuit board 10, the IC connection probe 15 to which the hold signal from the tester 14 is output is connected to each terminal 12 of the hold terminal C11 and the hold terminal 1.
3 and input this hold signal to the hold terminal 13. When the printed circuit board 10 is powered on, the circuit C11 receives a hold signal from the tester 14, and all of its output terminals become high impedance and are electrically inactivated. In this state, if a test signal is inputted from the tester 14 via the probe 15 to each terminal 12 of the IC1i with a hold terminal, only the test signal from the tester 14 will be inputted to each terminal of this IC11. , tester 14
There is no risk of conflict between the test signal of the IC and the output signal of the IC with a hold terminal, causing runaway of the circuit on the printed circuit board or destruction of the circuit elements.

そして、テスタ14によるプリント基板10の゛回路の
デバッグが終了したらプリント基板10の電源を切り、
その後、IC接続用プローブ15をはずして、デバッグ
が完了することになる。
After the tester 14 has finished debugging the circuit on the printed circuit board 10, the power to the printed circuit board 10 is turned off.
Thereafter, the IC connection probe 15 is removed and debugging is completed.

このように、プリント基板10の実装済みICとしてホ
ールド端子付きIC11を構成し、テスタ14からの試
験信号に先立ってホールド信号を前記工C11のホール
ド端子13に入力して当該工C11の出力端子をノ・イ
インピーダンスにすることにょ如、この工C11は、ホ
ールド状態となってテスタ14の試験信号とホールド端
子付き工C1lの出力信号が競合せず、プリント基板1
0上にホールド端子付き工C11を実装したままでプリ
ント基板のデバッグを行なうことができる。
In this way, the IC 11 with a hold terminal is configured as the mounted IC on the printed circuit board 10, and the hold signal is inputted to the hold terminal 13 of the device C11 prior to the test signal from the tester 14, and the output terminal of the device C11 is controlled. By setting the impedance to zero, this circuit C11 enters a hold state, and the test signal of the tester 14 and the output signal of the circuit C1l with a hold terminal do not conflict, and the printed circuit board 1
The printed circuit board can be debugged with the hold terminal C11 mounted on the board.

以上説明したように本発明の試験方法によれば、プリン
ト基板のハードウェア上のデバッグを行なう際にテスタ
からの信号を工Cソケットを介することなく基板上に実
装されたICの端子を通じて直接入力し得るので、従来
のようなICソケットの実装による工数の増加やフラッ
クスなどによる接触不良がなくなり、製品の組立作業の
簡素化や品質の向上がはかれる効果がある。
As explained above, according to the test method of the present invention, when debugging the hardware of a printed circuit board, signals from the tester are input directly through the terminals of the IC mounted on the board without going through the C socket. This eliminates the increase in man-hours and contact failures caused by flux, which are required in the conventional IC socket mounting process, thereby simplifying product assembly work and improving quality.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のプリント基板の試験方法を示す説明図、
第2図は本発明によるプリント基板の試験方法の一実施
例を示す説明図である。 10・・・・プリント基板、11・・・・ホールド端子
付き工C(集積回路)、13・・・・ホールド端子、1
4・・・・テ哀夕(外部試験装置X15・・・・IC接
続用プローブ、16・・・・ホールド信号出力端子。 =7−
Figure 1 is an explanatory diagram showing a conventional printed circuit board testing method.
FIG. 2 is an explanatory diagram showing an embodiment of the printed circuit board testing method according to the present invention. 10...Printed circuit board, 11...C with hold terminal (integrated circuit), 13...Hold terminal, 1
4...External test equipment X15...IC connection probe, 16...Hold signal output terminal. =7-

Claims (1)

【特許請求の範囲】[Claims] 複数の集積回路を実装して構成されたプリント基板にお
いて、外部試験装置からの信号を入力する集積回路にホ
ールド端子を設け、この集積回路のホールド端子を含む
端子に外部試験装置からの信号を入力するプローブを接
続し、外部試験装置からの試験信号に先立ってホールド
信号を前記ホールド端子に入力して当咳集積回路の出力
端子なハイインピーダンスにして電気的に非活性化した
後、試験信号を前記集積回路に入力してデバッグを行な
うことを特徴とするプリント基板の試験方法。
In a printed circuit board configured with multiple integrated circuits mounted, a hold terminal is provided on the integrated circuit that inputs the signal from the external test equipment, and the signal from the external test equipment is input to the terminal including the hold terminal of this integrated circuit. Connect the probe to be tested, input a hold signal to the hold terminal prior to the test signal from the external test equipment, make the output terminal of the integrated circuit high impedance, electrically inactivate it, and then apply the test signal. A method for testing a printed circuit board, characterized in that debugging is performed by inputting information to the integrated circuit.
JP56215636A 1981-12-25 1981-12-25 Testing method of printed board Pending JPS58111764A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56215636A JPS58111764A (en) 1981-12-25 1981-12-25 Testing method of printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56215636A JPS58111764A (en) 1981-12-25 1981-12-25 Testing method of printed board

Publications (1)

Publication Number Publication Date
JPS58111764A true JPS58111764A (en) 1983-07-02

Family

ID=16675680

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56215636A Pending JPS58111764A (en) 1981-12-25 1981-12-25 Testing method of printed board

Country Status (1)

Country Link
JP (1) JPS58111764A (en)

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