JPS58111453A - Synchronism detecting system - Google Patents

Abstract

PURPOSE:To improve the transfer efficiency of data, by comparing a part of a digital signal consisting of data and a synchronizing word with a preset synchronizing word and detecting the coincidence for a prescribed number of times or more consecutively. CONSTITUTION:In a transmitter 14, a 2-channel audio signal is converted 17 into a digital data of 12 bits and added with a control code of 3 bits, and then a synchronism word of 3 bits, and one block data is sequentially transmitted. In a receiver 22, the received data is inputted to a shift register SR23 of the same number of bits as that of data, overflow data is inputted to an SR26 of the same bit number as that of the synchronism word. The data from the SR26 is compared 28 with the data of a synchronism word register 29, and when they are coincident, the data is shifted for a prescribed bit number. When discident, the data are shifted by the number of bits different from the prescribed bit number and compared. When it is detected that the coincidence is performed for a prescribed number of times or more consecutively, the data of the SR23 is outputted through a gate circuit 27 after DA conversion 34.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization detection method, in which a part of a serially transmitted digital signal is compared with a synchronization word, and by detecting a continuous match, the power supply of the receiver detects the transmission. It is an object of the present invention to provide a synchronization detection method that can perform synchronization even if it is turned on or shut off regardless of the machine, and can increase data transfer efficiency by reducing the number of bits of a synchronization word.

When serially transmitting a digital signal obtained by changing the pulse code of an analog signal such as an audio signal or a video signal, there are cases in which power is turned on and off separately on the transmitting side and the receiving side.

Conventionally, there is a start-stop synchronization method as a method for detecting synchronization during serial transmission of digital signals. This is the bite shown in Figure 1.
When transmitter 1 and receiver 2 are both powered on and a serial transmission path is established, transmitter 1 continuously transmits, for example, a 1-bit stop code SP when there is no data. If you want to send 1 bit, the analogy is ``
o” start code ST followed by a predetermined number of bits of data! .

Transmit stop code SP and then start code 8T
, data (2), stop code, etc., and a digital signal having the configuration shown in FIG. 2 is transmitted. Receiver 2 is supplied with this digital signal, detects that the succession of stop codes 8P changes to start code ST, synchronizes, takes in data I, and reads the data between each data such as data ■, data ■, etc. A change from stop code 8P to start code 8T is detected and subsequent data is taken in while synchronizing. This start-stop synchronization method has a start code of 8T.

The stop code SP has a small number of bits, and when there is no data, it is widely used because the stop code SP can be transmitted continuously and data can be transmitted intermittently. If the power of the receiver 3 shown by the broken line is turned on while data is being transmitted to the
Since the receiver 3 cannot distinguish between the change of each bit in the data from "1" to "0" and the change from the stop code 5Prl to the start code 8T "0", synchronization cannot be detected and the receiver There is a drawback that the synchronous pull-in of step 3 is not performed.

In order to perform this synchronization, as shown in Figure 3, a digital signal is transmitted with a configuration in which a synchronization word 4 with a certain bit pattern is added in front of the name data such as data ■, ■, etc., and the receiver side There is a circuit shown in Figure 4 that separates data while maintaining synchronization. In Figure 4, input terminal 5
A digital signal having the configuration shown in FIG. 3 enters and is supplied to the shift register 6. Shift register 6 is data I
.

The number of stages is the same as the number of bits configuring The contents stored in the stages are supplied to the gate circuit 9 in parallel. The shift register 8 has the same number of stages as the number of constituent bits of the synchronization word 4, and shifts the supplied digital signal using a clock pulse from the clock generator 7, and the contents stored in each stage are transferred in parallel to the comparator circuit 1.
Supply to 0. The comparator circuit 1o is supplied with the same bit pattern as the synchronization word 4 in parallel from a synchronization word register 11 in which the synchronization word 4 shown in FIG. 3 is stored in advance. Here, the digital signal is sequentially shifted through the shift registers 6.8, and when the stored contents of the shift register 8 match the synchronization word 4 stored in the synchronization word register 11, the comparison circuit 10 supplies a match signal to the gate circuit 9. do. The gate circuit 9 supplies the stored contents of the shift register 6, that is, the data, to the DA converter 12 only when this match signal is supplied, and the data of this digital signal is outputted from the output terminal 13 after being converted into an analog signal. Ru.

In such a case, the comparator circuit 10 outputs one matching signal Ct
In order to prevent tI from being transmitted, synchronization word 4 must have a pit pattern that data cannot take, and it requires the same number of bits as the data or one bit more than that, which may result in extremely poor data transfer efficiency. There is a drawback. For this reason, the transmission speed is 1 Mbit/sea like the optical fiber system.

10 Mbit/sec, and the latter is approximately 2 times the former.
If it costs twice as much, it will cost 10% more due to poor data transfer efficiency.
There may be cases where it is necessary to use a 0 Mbit/sec system.

The present invention eliminates the above-mentioned drawbacks, and an embodiment thereof will be described with reference to FIG. 5 and subsequent figures.

FIG. 5 shows a block diagram of one embodiment of the synchronization detection method according to the present invention. In the same figure, 14 is a transmitter, and 15 is a transmitter.
is an input terminal to which the 2D Yannel audio signal is input.

The two-channel audio signal is amplified for each channel by an amplifier 16 and then supplied to an AD converter F17. A.D.
The converter 17 samples the audio decoding of each channel at a sampling frequency of 33 kHz, encodes it with the input bipolar 11 stepwise offset binary as shown in Table 1, and converts it into an O±IOV analog signal. converts the audio signal into a 12-bit digital signal.

Table 1 Also, the digital converter 17 adds a 3-bit control code to the 12-bit first channel and 12-bit second channel digital signals to make a total of 27 bits of data m, and then converts this data in parallel. The signal is supplied to and set in a shift register 18 having a 27-stage configuration. Further, the synchronization word register 19 supplies and sets the synchronization word (2) consisting of 3 bits and 1 bit to the shift register 20 having a 3'R' configuration at the same timing as the above-mentioned data setting. Shift register 18.2
A clock pulse is supplied from the clock generator 21 to the shift register 1820, and the overflow of the shift register 18 is supplied to the shift register 2°, and the shift register 1820 shifts the contents of each storage, and the overflow of the shift register 18 is supplied to the shift register 2°, and the shift register 2o supplies the clock pulse to the 6th shift register 2o. The 30-bit digital signals shown in the figure forming one block are sequentially extracted and transmitted.

This digital signal is transmitted through a serial transmission line and sent to the receiver 2.
The signal is supplied to the shift register 23 of No. 2.

When the receiver 22 is powered on, the clock generator 24
261C is supplied to shift register 23.261C via normally closed switch 25. The shift register 23 has 27 stages, which is the same number of bits as the data ■, and shifts the incoming digital signal using clock pulses, and transfers the overflow to the shift register 2.
6, and also supplies the contents stored in each stage to the gate circuit 27 in parallel. In addition, the shift register 26
has a 3-bit configuration, which is the same as the number of bits of the synchronization word (2), and shifts the digital signal from the shift register 23 using a clock pulse, and supplies the contents stored in each stage to the comparator circuit 28 in parallel.

The comparison circuit 28 is supplied with the synchronization word ■ from the synchronization word register 29, and this comparison circuit 28 synchronizes with the contents stored in the shift register 2'6 every time 30 clock pulses from the clock generator 4 arrive. The word ■ is compared, and when all bits match, a high-level pulse is generated as a match signal and supplied to the count input terminal of the counter 30 and one input terminal of the AND circuit 33, and when they do not match, a high-level pulse is generated as a match signal. The counter 30 generates a pulse of
゜Each reset terminal of flip 70 tube 31 and monostable multivibrator (hereinafter referred to as "mono multi") 3
Supply to 2. The counter 30 is reset to 0 by the pulse of this mismatch signal, and the Q terminal output of the flip-flop becomes a low level, which is supplied to the other input terminal of the AND circuit 33, and the monomulti 32 is triggered for approximately one clock period. A pulse with a pulse width of is generated and supplied to the switch 25. The switch 25 is opened for a period of this pulse width, cuts off the clock pulse from the clock generator 24 by one pulse, and is closed again.

As a result, after the shift registers 23 and 26 have shifted 29 bits, the next comparison is performed by the comparator circuit 28.

Comparisons are performed sequentially in this manner, and when a match signal pulse is generated, this pulse is counted by the counter 30, and after the shift registers 23-26 have shifted one block by 30 bits, the comparison is performed again. This comparison circuit 2
When a match signal is output from 8 consecutively, the counter 30 repeats counting, and the counting capacity of the counter 30 (for example, several tens)
When the pulse exceeds wo, the overflow pulse is supplied to the set terminal of the flip-flop 31 and
The Q terminal output of becomes high level, which is the AND circuit 3.
3. AND circuit 33 is flip-flop 3
After the Q terminal output of No. 1 becomes high level, a high level pulse which is a match signal from the comparator circuit 28 is passed through and supplied to the gate circuit 27. Only when a match signal is supplied, the gate circuit 27 converts each bit constituting the storage contents of the shift register 23, that is, the data .
4, where it is converted into analog audio signals of the first channel and the second channel, and outputted from the output terminal 35.

Here, if an analog audio signal is supplied from the input terminal 15, this audio signal changes every time it is sampled, so the bit pattern of the data ■ changes, and the bit pattern of the data ■ changes at a certain position among several ten consecutive pieces of data ■. The same bit pattern as the synchronization word ■ never exists, and erroneous synchronization detection will not be performed. Furthermore, when no audio signal is supplied from the input terminal 15, the audio signal voltage supplied to the amplifier 16 is o, ooooo v for each channel, but it varies by ±0.0049 depending on the transistors, resistors, etc. that constitute the amplifier 16. Random noise with a value exceeding V is mixed and supplied to the AD converter 17. Here, the AD converter 17 rolls < o, oooo v as shown in Table 1.
lllllllllllJ, -0,0049Vor1
To convert it to 00000000000J, even the sound -
Even when no signal is supplied, all bits of the first channel and second channel digital signals in the data (1) are inverted at random, so that erroneous synchronization detection will not be performed.

In addition, the sampling frequency is 33 kHz, or 30 μS.
Sampling is carried out once every 15 days, and each sampling consists of 3 bits of synchronization word, 127 bits of data, 3 bits in total.
A 0-bit digital signal is generated. Therefore, the transmission speed of this digital signal is 0.99 Mbit.
/see (0,99X10'=30X33X10")
becomes. In this way, the number of bits in the synchronization word ■ is small and the data transfer efficiency is high, so when transmitting using an optical fiber system, the transmission speed is low and the transmission speed is 1 Mbit/Mbit.
see's system can be used.

The content of the data m to be transmitted may be an audio signal or the like other than an audio signal, and the number of bits constituting each of the data ■ and the synchronization word ■ is arbitrary, and the number of bits of the synchronization word ■ is determined by the number of bits when the counter 30 overflows. (Ill ”””';
'l:.

- It can be shortened to 1 bit by increasing the number of times it is counted, and is not limited to the above embodiment. Furthermore, the serial transmission path may be wired, wireless, or the like.

As described above, the synchronization detection method C according to the present invention serially transmits a digital signal that constitutes a block of a predetermined number of bits by at least data consisting of a signal obtained by AD converting an input analog signal and a synchronization word. A part of the synchronization word is compared with a preset synchronization word, and when they match, the digital signal is shifted by a predetermined number of bits, and when they do not match, the digital signal is shifted by a number of bits different from the predetermined number of bits, and then the above comparison is performed. Since the data is retrieved by detecting a match more than a certain number of times, the receiver can be synchronized even if the power to the receiver is turned on or off independently of the transmitter, and the number of bits in the synchronization word can be reduced. The data transfer efficiency is high, which makes it possible to use an inexpensive transmission system, and the bit pattern of the AD-converted signal changes due to random noise when the input analog signal is not supplied. It has the advantage of not causing erroneous synchronization even when operated manually.

[Brief explanation of the drawing]

Fig. 1 is a diagram for explaining the start-stop synchronization method, and Fig. 2 is an example of a digital signal transmitted by the method shown in Fig. 1.
3 is a block diagram of an example of a digital signal transmitted using the conventional synchronous detection method. FIG. 4 is a block diagram of an example of the conventional synchronous detection method. FIG. 6 is a block diagram of one embodiment of the method of the present invention, and is a block diagram of an example of a digital signal transmitted by the method of the present invention. 14...Transmitter, 15...Exposure input terminal, 16...Amplifier, 17...@AD converter, 18, 20, 23
. 26...Shift register, 19,29"...Synchronization word register, 21,24.e.clock generator, 22
...Receiver, 25.Switch, 27.Contest gate circuit, 28.Φ.Comparison circuit, 30.Counter, 3
10・Flip-flop, 32・Kite・Monomulti, 33
-...AND circuit, 34-...DA converter, 35...
Output terminal. Fig. 1 Fig. 2 轡IV'l --chi Fig. 3 Fig. 4 Fig. 6 Persimmon opening-

Claims (1)

[Claims] (1) Serially transmit a digital signal that constitutes a block of a predetermined number of bits by at least data consisting of a signal obtained by AD converting an input analog signal and a synchronization word, and transmit a part of the digital signal and a preset synchronized word. When they match, the nuclear digital signal is shifted by the predetermined number of bits, and when they do not match, the nuclear digital signal is shifted by a number of bits different from the predetermined number of bits. A synchronous detection method that uses cough data as a signature. +2) The synchronization detection method according to claim 1, wherein the bit pattern of the 111 A/D converted signal is assimilated by random noise when the input analog signal is not supplied.