JPS6397936U - - Google Patents

Info

Publication number
JPS6397936U
JPS6397936U JP19129886U JP19129886U JPS6397936U JP S6397936 U JPS6397936 U JP S6397936U JP 19129886 U JP19129886 U JP 19129886U JP 19129886 U JP19129886 U JP 19129886U JP S6397936 U JPS6397936 U JP S6397936U
Authority
JP
Japan
Prior art keywords
synchronization signal
frame synchronization
bit
speed clock
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19129886U
Other languages
Japanese (ja)
Other versions
JPH0646115Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986191298U priority Critical patent/JPH0646115Y2/en
Publication of JPS6397936U publication Critical patent/JPS6397936U/ja
Application granted granted Critical
Publication of JPH0646115Y2 publication Critical patent/JPH0646115Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の実施例を示すフレーム同期信
号検出回路のブロツク図、第２図は従来のフレー
ム同期信号検出回路のブロツク図、第３図は第１
図の回路の動作を示すタイミングチヤートである
。 １，３……シフトレジスタ、２……同期パター
ン記憶部、４……高速クロツク発生器、５……カ
ウンタ、６……判定回路、７……マスタクロツク
発生器、８……クロツク再生回路、Ｇ１〜Ｇ３１
……排他的ＯＲ回路。 FIG. 1 is a block diagram of a frame synchronization signal detection circuit showing an embodiment of the present invention, FIG. 2 is a block diagram of a conventional frame synchronization signal detection circuit, and FIG.
3 is a timing chart showing the operation of the circuit shown in the figure. 1, 3...Shift register, 2...Synchronization pattern storage section, 4...High speed clock generator, 5...Counter, 6...Judgment circuit, 7...Master clock generator, 8...Clock regeneration circuit, G1 ~G31
...Exclusive OR circuit.

Claims (1)

【実用新案登録請求の範囲】 フレーム同期信号と定められた同期パターンと
をビツト毎に照合する照合手段と、前記照合によ
る一致または不一致のビツト数を計数するカウン
タと、前記カウンタの計数値によつて相互の等価
的な一致を判定する判定回路とを備えたフレーム
同期信号検出回路において、 前記各ビツトの照合結果を全ビツトについて順
次カウンタに取出すために、通信のビツトレート
に基づいて高速クロツクを発生して前記照合手段
に与えるマスタクロツク発生器と、 フレーム同期信号に同期してその各ビツトのデ
ータを順次取出して前記照合を行うために、フレ
ーム同期信号のビツト数以上の所定の分周比をも
つて前記高速クロツクを分周して低速クロツクを
発生して前記照合手段に与えるクロツク再生回路
とを設けてなる フレーム同期信号検出回路。[Claims for Utility Model Registration] A collation means for collating a frame synchronization signal and a predetermined synchronization pattern bit by bit, a counter for counting the number of matching or non-coincident bits resulting from the collation, and In the frame synchronization signal detection circuit, the frame synchronization signal detection circuit is equipped with a determination circuit that determines whether each bit is an equivalent match. and a master clock generator having a predetermined frequency division ratio greater than or equal to the number of bits of the frame synchronization signal in order to perform the verification by sequentially extracting the data of each bit in synchronization with the frame synchronization signal. and a clock reproducing circuit which frequency-divides the high-speed clock to generate a low-speed clock and supplies the generated low-speed clock to the collation means.
JP1986191298U 1986-12-12 1986-12-12 Frame sync signal detection circuit Expired - Lifetime JPH0646115Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986191298U JPH0646115Y2 (en) 1986-12-12 1986-12-12 Frame sync signal detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986191298U JPH0646115Y2 (en) 1986-12-12 1986-12-12 Frame sync signal detection circuit

Publications (2)

Publication Number Publication Date
JPS6397936U true JPS6397936U (en) 1988-06-24
JPH0646115Y2 JPH0646115Y2 (en) 1994-11-24

Family

ID=31145307

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986191298U Expired - Lifetime JPH0646115Y2 (en) 1986-12-12 1986-12-12 Frame sync signal detection circuit

Country Status (1)

Country Link
JP (1) JPH0646115Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101491651B1 (en) * 2013-08-14 2015-02-09 (주)에프씨아이 Method And Apparatus for Fast TMCC Data Acquisition

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58111453A (en) * 1981-12-24 1983-07-02 Victor Co Of Japan Ltd Synchronism detecting system
JPS58177049A (en) * 1982-04-08 1983-10-17 Fujitsu Ltd Detecting system of frame synchronizing pattern
JPS59221046A (en) * 1983-05-30 1984-12-12 Nec Corp Synchronizing word detecting circuit
JPS61219235A (en) * 1985-03-25 1986-09-29 Fujitsu Ltd Unique word detecting circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58111453A (en) * 1981-12-24 1983-07-02 Victor Co Of Japan Ltd Synchronism detecting system
JPS58177049A (en) * 1982-04-08 1983-10-17 Fujitsu Ltd Detecting system of frame synchronizing pattern
JPS59221046A (en) * 1983-05-30 1984-12-12 Nec Corp Synchronizing word detecting circuit
JPS61219235A (en) * 1985-03-25 1986-09-29 Fujitsu Ltd Unique word detecting circuit

Also Published As

Publication number Publication date
JPH0646115Y2 (en) 1994-11-24

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