JPS602820B2 - Code reception method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reception method that reduces the influence of noise or noisy signals in start-stop synchronization or bit-synchronization code communication.

Generally, a start-stop synchronization signal consists of a certain number N of information codes 3 (D,, ○2, D3...DN) between a start code 1 (ST) and a stop code 2 (SP), as shown in Figure 1a. ).

Taking the binary NRZ (non-return zero) equal-length code system as an example, each code has the same length as shown in diagram b, and its value is either "1" or "0". Normally, the received signal has a start code of ``0'', a stop code of ``1'', and an information code of 3 (D, D2, ...DN) of ``1'' or ``1'' depending on the bit information, as shown in Figure 1b. Section 4 with no 0c signal
A method is adopted in which the value is held at "1". Also,
FIG. 2 is a block diagram of a conventional circuit for receiving the above signals and extracting digital information, and FIG. 1c shows a time chart of the clock generating circuit used in this case.

The received signal 5 (FIG. 1b) is input as a serial code.
Also, 6 is a start judgment circuit, the signal changes from "1" to "0".
After At/2 has elapsed since the value falls, it is determined that the value is "0", a start determination signal 7 is generated, and the clock generation circuit 8 is activated. Note that 9 is the reception level detection signal,
As a result, the start determination circuit 6 and the clock generation circuit 8
Release the reset hold. The clock generation circuit 8 is composed of a flip-flop 10, a gate synchronized oscillator 11, and a counting circuit 12 as shown in FIG.
+1 ku. A clock pulse 13, a clock gate 14 for the period in which the flip-flop 10 is set, and an N+1 pulse 15 are generated. Normally, the clock gate 14 inhibits the start determination circuit 6. The clock pulse 13 drives the shift register 16 of FIG. 2a,
The input signal 5 is sampled approximately at the center of the code, and the information code 3 (D
, D2, ...DN) and the SP bit "1" 0100 million are sequentially read into the shift register 16. Therefore, the shift register 16 outputs its output terminal 17- when N+1 clocks are completed. 1,17-2,...,171 (N11
) has stop code 1 (SP) and information code 3 (DN, D
N-..., D2, D,) appears. These are transferred to the output register 19 by opening the gate circuit 18 with the N+1 pulse 15 which is generated a little later than the N11th clock pulse. ) in parallel. 20 is a sign verification circuit that accumulates the "1" value of "0" every time the information code 3 (D,, D2, ...DN) of the input signal 5 is received in synchronization with the clock pulse 13. Then, a test based on a preset code configuration, such as a parity test or a constant mark test, is performed, and after the N+1 pulse 15 is completed, the pass/fail is determined, and a test signal 21 is output.

Note that since the stop code 2 (SP) in the N11 section of the shift register 19 should originally be "1", it is possible to perform a signal length test based on a preset code configuration. As is clear from the above explanation, after the reset hold is released by the bell detection signal, the receiving circuit is activated by the first "0" signal with a width of At/2 or more, and generates N+1 clock pulses based on this signal. Code reception is performed in synchronization with this.

However, although this method works normally when there is no noise signal at the time of no information signal 4 (Fig. 3a),
Start code 1 (ST) after reset release as shown in Figure 3b
If a noise signal 22 is mixed between the stop code 2 (SF) and the start code 1 (ST) within (N12)Δt before
, D2, .

Generally, a signal is transmitted as a modulated wave through a wired or wireless circuit, and a demodulation circuit has a function of automatically adjusting the gain for level fluctuations of about 3 WB. Therefore, when there is noise that is two generations older than the signal, if a normal signal arrives, the gain will be suppressed and it will not be detected, but the section where there is no signal will be detectable and will be amplified to a level. In particular, when using a wireless line that does not have a high S/N ratio, the signal level must be detected due to pulse noise, interference, etc.
There is a high possibility of receiving a value. Also, even with wired lines, there is a problem in that if pulse noise crosstalk or the like mixes between normal signals, normal information cannot be received. In order to solve the above-mentioned problems, the present invention generates a clock synchronized with the weak noisy signal once the receiving circuit is activated. , the clock has been improved so that it can synchronize the clock with a later strong normal signal and extract only the normal signal even if the signal is zero, and the details will be explained below.

FIG. 4 shows an example of the configuration of the first embodiment of the present invention, and a shows an example in which the information code 3 can be taken out in parallel to the output register 26 by inputting the asynchronous reception signal 5 and the signal level detection signal 9. This is a possible circuit.

The F/F symbol in the figure is a flip-flop, and the terminal symbol P operates at the falling edge of a positive pulse.
6A is a start determination circuit, 8A is a clock generation circuit which is a feature of the present invention, 16A is a shift register that sequentially stores serial reception signals, and 18 is a gate circuit for transferring the contents of the shift register 16A to the first output register 19'. , 22 is a circuit for verifying the sign of the first output register 19, and 24 is a gate circuit for transferring the contents of the first output register 19 to the second output register 26 by the sign verification pass pulse 25.

The routine operation of the above circuit will first be described with reference to FIG. 5, which is a waveform diagram of a received signal free from noise and interference.

6A is a start judgment circuit, and the input is "1" as shown in Figure 5a.
falls to "0,100,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000;

6A is not only the start code 1 (ST) but also the information code 3
Even if the bit is "0" in (D,, D2, . . . DN), the start determination signal 7A is generated.

The details of the clock generation circuit 8A are as shown in FIG.
It consists of a synchronous oscillator 11A, a counting circuit 12A, an output flip-flop 28, and an output gate circuit 29, the details of which are shown in FIG. Flip-flop 10A is set by start signal 7A when detection signal 9 is present, and generates clock gate pulse 14A. 11A is a synchronous oscillator, and during the period when the clock gate pulse 14A exists, the rise of the clock gate pulse 14A and the start judgment signal 7 are provided.
This circuit generates a clock pulse 13A with a period Δt in synchronization with A and delayed by Δt from these signals.The details of the circuit are shown in FIG. 33, 33A, gate synchronous oscillators 35, 35A, and an OR gate 37 for synthesizing the outputs, and its operation will first be described for the case where there is an input as shown in FIG. 5a.

When the flip-flop 10A is in the reset state, the clock gate pulse 14A has a "0" value and the flip-flop 3
3 is set, flip-flop 33A is in reset state,
The gate synchronous oscillators 35 and 35A do not operate because their inputs are inhibited. Furthermore, the clock gate pulse 14A is set to "1" in the first start judgment signal 7A-IZ in FIG. 5b.
When the value is reached, the flip-flop 33 sets and holds the value.
The flip-flop 33A is reset and held, and the inhibition of the inputs of the gate synchronous oscillators 35 and 35A is released. Immediately after release, 342 has a value of "1" and 3 as shown in Figure 5b.
4A becomes a "0" value, the gate synchronous oscillator 35 operates, and its output is applied to the input 36 of the OR gate 37 with clock pulses at intervals Δt. Next start judgment signal 7A
12 passes through the gate circuit 31A to the flip-flop 33A.
At the same time as setting , the delay circuit 32 resets the flip-flop 33 with a delay of time y. As a result, the gate synchronous oscillator 35A is set to "1" by the start determination signal 7A-2.
It operates in synchronization with 34A, which has reached the value 34A, and generates a clock pulse shifted by an interval Δt after a time Δt at the input 36A of the OR gate 37. The delay time 7 of the delay circuit 32A is <
When selecting Δt (for example, 7=Δt/2) to produce an output at the enemy 36A, the flip-flop 33 has already been reset, and the gate synchronous oscillator 35 is in an inactive state and does not produce an output at the enemy 36. Similarly, the flip-flop 33 is set in synchronization with the next start determination signal 7A-3, and when the gate synchronous oscillator 35 is in the operating state, the flop 7A-3 is set.
After a time, the flip-flop 33A is reset and the gate synchronous oscillator 35A becomes inactive, and after a time At, a clock pulse with an interval Δt is generated from the 36 side. Clock pulses 36 and 36A are input to an OR gate circuit 37. As is clear from the above explanation, the output terminal 13A of the synchronization gate circuit 11A is synchronized with the start judgment signal 7A every time the start judgment signal 7A is input, and after the time △t, the output end 13A of the synchronization gate circuit 11A is synchronized with the start judgment signal 7A.
Generates a clock pulse. The clock pulse 13A drives the shift register 16A and input signal 5 "1", "
0'' value and calculate it one by one. The counting circuit 12A counts the clock pulses 13A, and when the counted value becomes equal to the preset received code length N', it sets the flip-flop 28 with an N pulse output 15A. fritsub flop 2
8 is set, the gate circuit 29 is opened and the output signal of the gate circuit 29 is the N11th and subsequent clock pulses. This (N11) pulse 23 is the gate 18
The contents of the shift register 16A are transferred to the first shift register 19. Reference numeral 22 denotes a code verification circuit which is activated by the (N+1<) pulse 23, inputs the contents of the first shift register 19 in parallel, and performs verification based on each code configuration.

Code construction rules include parity, constant mark, addition of ``1'', cyclic code, etc., and when it is constant, it takes some time 7
c. In the present invention, it is necessary that ↑c and △t. Especially if you use a cyclic code? c.
1 of code length N in between. Requires a sap clock at the level of a needle sound. Now △t=0.2 skin s (equivalent to 4800 baud), N=
20, the interval between the subclocks requires about 61 seconds, which is a value that can be easily achieved with current technology. Note that during the sign verification, it is also verified that the (N11) bits are a stop sign, that is, a value of "1". As described above, if the result of the sign test is passed, the pass pulse 205 is generated, the gate circuit 24 is opened, and the information code 3 (D,, D2, ... DN) of the contents of the shift register 19 is read. It is transferred to the second output register 26. The pass pulse 25 also serves as a reset pulse to reset the flip-flop 10A in the clock generation circuit 8A, and sets the clock gate pulse 14A to "0" to complete one code reception. The above is a case where the signal is received normally, but the information code 3 (D,, D2
,...DN) occurs during transmission and fails the test at N+1 pulse, the 0 pass pulse is not generated, the reception is not completed once, and clock pulses continue to be generated.
Signals continue to be input to the shift register 16A.

In this case (N11<), a pulse continues to appear in the pulse 23, and the contents of the shift register 6 are transferred to the first output register 19 every clock pulse, and the sign verification continues. In this case, bits 1 to N of the shift register 16A are not information bits D, to DN, but for example, if sent once after N+1, D2 to D
Since N+ is entered, if it were to pass the test, the output information would be incorrect. Therefore, it is necessary to provide the codes D and ~DN with a verification function that will sufficiently reduce the probability of detecting a conspiracy, but in addition to a simple parity test, it is possible to use constant marks, addition of total numbers, cyclic codes, transportation verification, etc. as appropriate. With current technology, it is possible to sufficiently reduce the detection of fraud. However, if the clock gate pulse 14A remains at "1", problems may occur, so as shown in FIG.
When the count value of 2A exceeds N0m, (N+m) pulse 3
0 is generated to reset the flip-flop 10A, and in addition to the sign verification circuit 22 as shown in FIG. As a modification of this embodiment, the flip-flop 10A may be provided with a timer function so that it is automatically reset at a time corresponding to (N+m)Δt. This can be easily realized by making the flip-flop 10A a one-shot multi-chip and setting its pulse width to (N0m)Δt. In the above embodiment, a clock pulse forcibly synchronized with the input signal is generated every time the input signal falls from the "1" value to the "0" value, and the number of clocks is not limited to the number of sign bits N'. Even if the number is N or more, it can be received.

Therefore, even when there is noise in front of the signal, such as 22 in FIG. 3b, and the conventional circuit cannot receive the signal, the signal can be received.
That is, as shown in FIG. 3c, the clock pulse 23A is generated in synchronization with the start determination pulse 7A, which is synchronized with the falling edge of the input signal. In addition, the code check is performed when (N+1) pulses 23 are generated when the number of clock pulses 13A exceeds (N+1) from the start, but if the code has a sufficient verification function, the section that is not synchronized with the information code 3 can be checked. It can be expected that there is a small possibility that a pulse passing the test will occur when (3) is met. Therefore, even if there is noise 22 as shown in Fig. c, it is possible to receive the start-stop synchronization signal. Note that if the signal is not a pulse noise like 22 but is lower in level than the signal but still detectable, the signal may be continuously received. In this case, even if a clock is generated in synchronization with a weak signal, if a regular strong signal is input later, the clock will be generated in synchronization with the strong signal, and the automatic gain control circuit will suppress the weak signal, resulting in a normal code string. is received, making stable reception possible. In addition, in the case of a step synchronization signal, in the conventional method, it was necessary to synchronize the clock frequency of transmission and reception with high accuracy so that the clock pulse and code position 0 do not deviate up to N bits in synchronization with the initial start judgment, but with this method. In this case, it is sufficient to make the accuracy so that the code bits adjacent to each other change from "1." to "0."

Therefore, if care is taken to ensure that "1" or "0" do not continue for a long time when configuring the code, there is an advantage that even in the case of an NRZ signal, there is no need to precisely synchronize the transmitting and receiving clocks of the RZ signal synchronizer. Next, a second embodiment of the present invention will be described in detail with reference to FIGS. 6 and 7.

FIG. 6 is a waveform diagram, and FIG. 7 is a block diagram. The parts that overlap with those of the first embodiment described above will be omitted, and only the different parts (the parts surrounded by broken lines) will be explained. The first embodiment deals with an asynchronous equal-length NRZ (non-return zero) signal as shown in FIG. 2
This is an example.

The input signal 38 remains "0" for a certain period of time as shown in FIG. 6a.
After the value continues, a start code IA (ST) is input. This input signal 38 is input to a sign determination circuit 39 and a start determination circuit 6A. Here, the sign 0 determination circuit 39 drives the flip-flop 10A with the signal 14A in FIG.
”, is converted into a “0” signal, and a clock pulse 13A is generated every time the conversion is completed. Note that since the RZ long/short code is bit synchronized, an oscillator for start/stop synchronization is not required. On the other hand, the start determination circuit 6A determines the start of the input signal 38 and sets the gate circuit of the flip-flop 10A. Also, the signal 40 of "1/0" is the clock pulse 1.
3A, the signals are sequentially read into the shift register 16, the gate circuit 18 is opened by the (N+1<) pulse 23, which is a feature of this embodiment, the signals are transferred to the first shift register 19, and the sign is verified by the verification circuit 22.

When the test passes, the gate circuit 24 is opened by the pass pulse 25, the output of the shift register 19 is transferred to the second shift register 26, and the flip-flop 10A is reset by the pass pulse 25 to receive one reception. finish.
If the test fails, flip-flop 10A is not reset and continues to receive up to (N+m) pulses 30. In this case, the flip-flop IDA may be provided with a timer function instead of the (N10m) pulse 30. If this embodiment is adopted under conditions where there is a lot of noise interference and interference, and signal level fluctuations at each station are large, even if there is noise or mixed signals, the level of the regular signal will be sufficiently higher than the noise or mixed signals when the signal is arriving. If these can be sufficiently suppressed by the AGC circuit, it will be possible to receive regular signals later. As explained above, the signal receiving system according to the present invention includes a clock circuit and an associated receiver housing that can receive a normal signal later in synchronization even if it malfunctions in synchronization with noise. Therefore, it will be most effective when used for receiving signals transmitted over a line with a lot of noise, ringing interference, and noise, especially on a wireless or wired line under relatively poor conditions. It is.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the start-stop synchronization signal, in which a shows the code structure, b shows the signal waveform, c shows the control signal necessary for the reception process, and Fig.
The figure shows the system diagram of the receiving circuit of the slave, and a shows the entire circuit b' and a part of the clock generation circuit. Fig. 3 is a waveform diagram explaining the drawbacks of the conventional system and the effects of the present invention, and a shows normal operation. 4 is a receiving circuit system diagram of the first embodiment of the present invention, where a is the entire circuit and b is a partial clock generation circuit. , c is a diagram showing a synchronous oscillator in circuit b, FIG. 5 is a waveform diagram explaining the operation of FIG. Fig. 6 is a waveform diagram explaining the second embodiment of the present invention, a shows the code structure and input signal, b shows the control signal necessary for the receiving process, and Fig. 7 is a receiving circuit diagram of the second embodiment. It is. 6,6A. ...Start judgment circuit, 8,8A...
・・・．・Clock generation circuit, 10, 10A, 28...
・Flip-flop, 11, 11A...Synchronization gate circuit, 12, 12A...Counting circuit. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] 1. A clock pulse generator that synchronizes with a preset start signal every time a code similar to a preset start signal is received when receiving an astop synchronization code, and a clock pulse generator that sequentially stores the received signal in synchronization with the clock pulse. and a code verification circuit that performs verification including stop codes after the accumulated number reaches the code length,
The code is characterized in that when a certain number of codes is reached, the code verification circuit is started, thereafter verification is performed for each code input, and when the verification is passed, the accumulated received codes are output and the clock pulse and the code verification circuit are stopped. Reception method. 2. In claim 1, when receiving a synchronization code, the received signal is sequentially input and accumulated using a clock pulse extracted in synchronization with each bit, and the verification is performed after the accumulated number reaches the code length. A code reception method characterized by the use of a code verification circuit.