JPS57201358A - Start-stop synchronous receiver - Google Patents

Start-stop synchronous receiver

Info

Publication number
JPS57201358A
JPS57201358A JP56085393A JP8539381A JPS57201358A JP S57201358 A JPS57201358 A JP S57201358A JP 56085393 A JP56085393 A JP 56085393A JP 8539381 A JP8539381 A JP 8539381A JP S57201358 A JPS57201358 A JP S57201358A
Authority
JP
Japan
Prior art keywords
circuit
pulses
baud rate
start bit
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56085393A
Other languages
Japanese (ja)
Inventor
Hidekazu Kudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56085393A priority Critical patent/JPS57201358A/en
Publication of JPS57201358A publication Critical patent/JPS57201358A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To improve reliability of circuits by making the number of detection pulses for start bit plural and thereby removing meaningless information caused by noise etc. CONSTITUTION:When data of series data line RD becomes a space state from a mark state, a start bit detection circuit 8 is operated. A baud rate counter 13 divides receiving clock according to baud rate of the data signal, and generates sampling pulses. A character length counter 15 detects the length of one character of the data signal, and a shift register 16 holds the series data and performs concession synchronous receiving by the sampling pulse generated. At this time, specified plural detection pulses are supplied from a pulse generating circuit 14 to the circuit 8.
JP56085393A 1981-06-03 1981-06-03 Start-stop synchronous receiver Pending JPS57201358A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56085393A JPS57201358A (en) 1981-06-03 1981-06-03 Start-stop synchronous receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56085393A JPS57201358A (en) 1981-06-03 1981-06-03 Start-stop synchronous receiver

Publications (1)

Publication Number Publication Date
JPS57201358A true JPS57201358A (en) 1982-12-09

Family

ID=13857517

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56085393A Pending JPS57201358A (en) 1981-06-03 1981-06-03 Start-stop synchronous receiver

Country Status (1)

Country Link
JP (1) JPS57201358A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5318904A (en) * 1976-08-05 1978-02-21 Oki Electric Ind Co Ltd Code receiving system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5318904A (en) * 1976-08-05 1978-02-21 Oki Electric Ind Co Ltd Code receiving system

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