JPS58111327A - Preparation of semiconductor power module - Google Patents

Preparation of semiconductor power module

Info

Publication number
JPS58111327A
JPS58111327A JP20915481A JP20915481A JPS58111327A JP S58111327 A JPS58111327 A JP S58111327A JP 20915481 A JP20915481 A JP 20915481A JP 20915481 A JP20915481 A JP 20915481A JP S58111327 A JPS58111327 A JP S58111327A
Authority
JP
Japan
Prior art keywords
alloy
power module
semiconductor power
heat
generated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20915481A
Other languages
Japanese (ja)
Inventor
Yoshihiro Suzuki
鈴木　芳博
Tadashi Minagawa
皆川　忠
Komei Yatsuno
八野　耕明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP20915481A priority Critical patent/JPS58111327A/en
Publication of JPS58111327A publication Critical patent/JPS58111327A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H01L23/4924—Bases or plates or solder therefor characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To remove the warpage or crack of substrate due to thermal fatigue by using a hard Cu alloy as an electrode plate or heat-sink. CONSTITUTION:A Cu 75%-Zn 25% alloy with hardness of 155Hv and a nickel plated alumina insulating plate in purity of 96% are soldered under the hydrogen ambient being heated up to 380 deg.C for five minutes using the solder of Pb95%- Sn5%. A semiconductor element, electrode plate, insulator and heat-sink are soldered at a time as described above. Thereby, even when module temperature rises after a module is operated and heat is generated on an element, any warpage or separation of substrate are not generated and crack is not generated on the insulator and accordingly a highly reliable module can be obtained.

Description

【発明の詳細な説明】 本発明は半導体パワーモジュールの製造法に係り、特に
、１５０Ｈｖ以上の硬度を有するＣｕ合金を電極板もし
くはヒートシンク板として用いることによプ、熱疲労に
よる基板のそりを除去した高信頼性のモジュールの製造
法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor power module, and in particular, by using a Cu alloy having a hardness of 150 Hv or more as an electrode plate or a heat sink plate, warpage of a substrate due to thermal fatigue is eliminated. The present invention relates to a method for manufacturing highly reliable modules.

従来、半導体モジュールに使用されている電極板あるい
はヒートシンク板には銅板もしくはニッケルめっきされ
た銅板が用いられている。しかし、周知のように、半導
体素子の高出力化が進むにつれて、素子の形状が大きく
なシ、それにと４ない、銅などの金属板あるいは絶縁板
などの形状も次第に大型化し、その結果、金属板の硬度
が低いと、動作時のヒートサイクルにより、これらの基
板や半導体素子の熱膨張率の差によシ、基板がはく離し
九シ、あるいは、クラックなどが生じたりする問題があ
り、そのため金属板としてＣｕ−Ｃ板またはＣｕ　−Ｉ
ｎ　Ｗａｒなどの適用が検討されている。Conventionally, copper plates or nickel-plated copper plates have been used as electrode plates or heat sink plates used in semiconductor modules. However, as is well known, as the output power of semiconductor devices progresses, the shape of the device becomes larger, and the shape of metal plates such as copper or insulating plates also gradually becomes larger. If the hardness of the board is low, there is a problem that the heat cycle during operation may cause the board to peel or crack due to the difference in thermal expansion coefficient between the board and semiconductor elements. Cu-C plate or Cu-I as metal plate
Applications such as n War are being considered.

本発明の目的は基板のそりあるいは割れをなく゛すため
に、ヒートシンク板あるいは電極板用として硬度の高い
Ｃｕ合金を用いる半導体パワーモジュールの製造法を提
供するにある。An object of the present invention is to provide a method for manufacturing a semiconductor power module using a Cu alloy with high hardness for the heat sink plate or electrode plate in order to eliminate warping or cracking of the substrate.

硬度が１５０Ｈマ以上のＣｕ合金を電極板あるイｔｉヒ
ートシンク板として用いることにより、使用時に半導体
モジュールの温度が上昇しても、基板のそりを低減し、
クツツクなどの発生を防止することができる。By using a Cu alloy with a hardness of 150H or higher as the heat sink plate with the electrode plate, even if the temperature of the semiconductor module rises during use, the warpage of the board can be reduced.
It is possible to prevent the occurrence of scratches and the like.

〈実施例１〉 硬度１５５）ＩＶのＣｕ７５％−２ｎ２５％合金（２５
，０Ｘ２５．０ＸＬＯ■）と、ニッケルめっきされた純
度９６％のアル建す絶縁板（２５，０Ｘ２５、ＯＸｏ、
６ｍ）とをｐｂ９５％−Ｂｎ５％のハンダを用い、水素
雰囲気中で３８０Ｃで５ｍ１ｎ７ＪＩＩ＋熱して、ハン
ダ接着した。その後、熱衝撃試験条件は一６５Ｃ〜１２
５Ｃでそれぞれ３６　ｍｉｎ保持し、試料を低温から高
温く交互に移動する際、室温でその都度５ｍ１ｎ保持し
た。まえ、基板のそりは単位長さく１）あた夛の鋼板の
凹の深さくｓｗ）で表示した。熱衝撃試験後のそヤは０
．０５■／ｃｍであシ、アルミナ基板にクラックの発生
は認められなかった。ただし、ハンダ接着前の銅板の凹
は０、０３　ｗｍ／ＩＭＩであつ九。<Example 1> Cu75%-2n25% alloy (25%) with hardness 155) IV
,0X25.0XLO■) and nickel-plated 96% purity aluminum insulation board (25,0X25,OXo,
6m) and 5m1n7JII+ were soldered together using 95% Pb-5% Bn solder and heated at 380C in a hydrogen atmosphere. After that, the thermal shock test conditions were 165C to 12C.
Each sample was held at 5C for 36 min, and when the sample was moved alternately from low temperature to high temperature, it was held at room temperature for 5 ml each time. Previously, the warpage of the board was expressed by the unit length (1) depth of the recess in the steel plate (sw). Soar after thermal shock test is 0
．． No cracks were observed on the alumina substrate at 0.05 cm/cm. However, the concavity of the copper plate before soldering is 0.03 wm/IMI.

〈実施例２〉 硬［１１０ＨＶのＣｕ９３％−Ｎ１％合金ヲ用いて、実
施例１と同じようＫして、耐熱衝撃性を調べ九。その結
果、熱衝撃試験後の凹はαｏ３■／ｃｍでらシ１アルミ
ナ基板にクラックの発生は認められなかった。<Example 2> Using a hard [110 HV Cu93%-N1% alloy], the thermal shock resistance was examined in the same manner as in Example 1. As a result, the concavity after the thermal shock test was αo3/cm, and no cracks were observed in the alumina substrate.

〈実施例３〉 硬度１７０ＨＶのｃｕａｏ％−Ｎｉ２５％−Ｚｎ１５％
合金を用いて、実施例１と同じようにして、耐熱衝撃性
を調べた。その結果、熱衝撃試験後の凹はα０５寵／ｃ
ｎｇであシ、アルミナ基板にクラックの発生は紹められ
なかった。<Example 3> Cuao%-Ni25%-Zn15% with hardness 170HV
Thermal shock resistance was examined in the same manner as in Example 1 using the alloy. As a result, the concavity after the thermal shock test was α05/c
No cracks were observed on the alumina substrate using NG.

〈実施例４〉 硬ｆｆ１５４ＨＶ（７）ＣｕＱ＆８３％−０ｒ１．１７
％合金合金いて、実施例１と同じようにして、耐熱衝撃
性を調べた。その結果、熱衝撃試験後の凹は０゜０６■
／３であり、アルζす基板にクラックの発生は認められ
なかった。<Example 4> Hard ff154HV (7) CuQ&83%-0r1.17
% alloy, and the thermal shock resistance was examined in the same manner as in Example 1. As a result, the concavity after the thermal shock test was 0°06■
/3, and no cracks were observed on the aluminum substrate.

〈実施例５〉 実施例１〜４における各鋼合金にニッケルめっきした基
板を用いて、以下実施例１と同じようにして、耐熱衝撃
性を調べた。その結果、各基板とも熱衝撃試験後の凹は
０．０３〜０．０５■／ｃｍでめシ、アルミナ基板にク
ラックの発生は認められなかった。<Example 5> Thermal shock resistance was examined in the same manner as in Example 1 using the nickel-plated substrates of each of the steel alloys in Examples 1 to 4. As a result, the concavities of each substrate after the thermal shock test were 0.03 to 0.05 .mu./cm, and no cracks were observed in the alumina substrate.

〈比較例１〉 硬１ｆ１１０Ｈマの鋼板を用いて、実施例１と同様にし
て、耐熱衝撃性を−ぺ九。その結果、熱衝撃試験後の凹
は０．５５ｗａ／ｃｍでおり、アルξす基板にクラック
が発生した。<Comparative Example 1> Using a steel plate with a hardness of 1f110H, the thermal shock resistance was tested in the same manner as in Example 1. As a result, the concavity after the thermal shock test was 0.55 wa/cm, and cracks occurred in the aluminum substrate.

Claims (1)

【特許請求の範囲】 １、メタライズされた半導体素子および絶縁板と金属板
とをＰｂ９０％以上含むハンダにょシ、一度に積層接着
することを％黴とする半導体パワーモジュールの製造法
。 ２、特許請求の範囲第１項において、金属板として、Ｃ
ｕ合金を便用することを特徴とする半導体パワーモジュ
ールの製造法。 ３、特＃’Ｆ！＋１１１求の範囲第２項においてＣｕ合
金がＣｕを主成分とし、Ｎｉ、ｚｎおよびＣｒの少なく
ともｌ種類の元素を含むことを特徴とする半導体パワー
モジュールの製造法。 ４、特許請求の範囲＄２項において、金属板の表面がＮ
ｉめっきされていることを特徴とする半導体パワーモジ
ュールの製造法。[Scope of Claims] 1. A method for manufacturing a semiconductor power module in which a metallized semiconductor element, an insulating plate, and a metal plate are laminated and bonded all at once using a solder containing 90% or more of Pb. 2. In claim 1, as the metal plate, C
A method for manufacturing a semiconductor power module characterized by convenient use of a u-alloy. 3.Special #'F! A method for manufacturing a semiconductor power module, characterized in that the Cu alloy has Cu as a main component and contains at least l elements of Ni, zn, and Cr in the second term of the range of +111. 4. In claim $2, the surface of the metal plate is N
A method for manufacturing a semiconductor power module characterized by being i-plated.
JP20915481A 1981-12-25 1981-12-25 Preparation of semiconductor power module Pending JPS58111327A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20915481A JPS58111327A (en) 1981-12-25 1981-12-25 Preparation of semiconductor power module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20915481A JPS58111327A (en) 1981-12-25 1981-12-25 Preparation of semiconductor power module

Publications (1)

Publication Number Publication Date
JPS58111327A true JPS58111327A (en) 1983-07-02

Family

ID=16568204

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20915481A Pending JPS58111327A (en) 1981-12-25 1981-12-25 Preparation of semiconductor power module

Country Status (1)

Country Link
JP (1) JPS58111327A (en)

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