JPS5810918A - Digital-to-analog converter - Google Patents

Abstract

PURPOSE:To realize the high speed of a titled converter and to decrease the scale of a storage circuit, by instantly determining a switching point from a digital signal of a part of an input code. CONSTITUTION:A control signal is supplied to a bus selector 6A from a sequencer B via a signal line 9C and the input terminal C is selected. Thus, an input code Din inputted from a terminal 1 is latched to a latch 8. Next, a bus selector 6B selects an input terminal B, drives an ROM5B and a readout output is transferred to an adder 4 and summed with the input code Din latched at the latch 8. A sequencer 7 discriminates whether the content of a digit corresponding to the most significant bit of an original DAC is 1 or 0 as the result of summing, and the obtained result is latched to the latch 8. This is respetitively done for the low-order biet number (m). When this processing is finished, the bus selector 6B selects an input terminals A, drives an ROM5A, and the readout result is summed to a code obtained with the said repetition.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is based on the so-called digital-to-analog conversion IIC, which is not satisfied in terms of accuracy but resolution, that is, does not satisfy linearity. Regarding the digital-to-analog converter (hereinafter abbreviated as DAO) that uses digital trimming to correct linearity and improve accuracy, the input code converter has been particularly improved to achieve high conversion speed. It is aimed at digital analogue converters and converters that are designed to reduce the size of memory circuits and reduce the size of memory circuits.

The inventors of the present invention have made a special request for the digitally trimmed D Todoro 0! In the j-/core JJ, the #Il digital-to-analog converter (
The output value of the lower digit (abbreviated as 0) and the output value of the 1-bin 4th of the digital input of the least significant digit of the first digital-to-analog converter (abbreviated as 0) as the output of the lower digit (/L8B
1s that produces a full-scale output that is always greater than the value of
l digital-to-analog converters; addition means for adding the outputs of the first digital-to-analog converter and the outputs of the second digital-to-analog converter to obtain an analog output signal; And the second digital-analog transformation! I! #t, so that the relationship between the digital input signal to the device and the analog output signal is linear.

Shifting the digital input signal by a predetermined value [obtained input;
- a code converter for inputting codes to the first and second codigital-to-analog converters.

Here, the upper DAO and the lower DAO can be composed of the original DAO, and an example of the characteristics of the J bit of the upper DAC is shown in Figure 1, and the output changes at the carry-over point of the input from the lower DAO to the upper DAO. always decreases.

In order to correct this characteristic to iJl [characteristic shown by the first IIK, K needs to perform a first-order code conversion.

That is, when the input code at the position where the correction amount is switched is J*'1+JQ g ""-.

When the input code is Q-Jo, the shift amount is 00 (total 0
), J.~J1, cl, .-1, and so on, and determine the shift amount from the input code.

It is necessary to add a correction amount corresponding to the shift amount to the input code.

In that case, input code JO”-Jl lJl~J31
The problem is to identify in which region the object is located. In principle, the input code is the switching point code Je + Jle JQ #-..., Jn
The code J (in which the input code is larger) is determined by successive comparisons, and the input code is in the area JQ-1-JQ.
can be identified as being in However, in the worst case, the number of times of this comparison operation is equal to the number of switching points Jq,
In other words, the number of times corresponds to the resolution of the upper DAO,
The above-mentioned D-0 has the drawback of requiring a long processing time. Yet again. The basic comparison operation can be realized by reading data indicating the switching point from the storage circuit, taking the complement of I of that data, and adding it to the input code.
Access to the memory circuit, inversion of successive data, and one-time addition processing are required, making the total time even longer.1 or more is a major hindrance to shortening the DA conversion time of D^0 as proposed above. It becomes. In addition, the configuration of the logic circuit for performing such processing becomes complicated, and there is a problem in that the storage capacity of the storage circuit becomes particularly large.

Therefore, one object of the present invention is to solve the above-mentioned problems and to increase the DΔ conversion speed by making it possible to immediately determine the switching point from a digital signal of a portion of the input code.
Moreover, it is an object of the present invention to provide a digital-to-analog converter in which the scale of the memory circuit is reduced.

In order to achieve such an object, the present invention includes a first digital-to-analog converter that generates an output of the most significant digit, and a digital input of the least significant digit of the first digital-to-analog converter as an output of the least significant digit. Output value for 4th l bin of (/
a first digital-to-analog converter that generates a full-scale output that is always larger than the value of L8B; adding means for obtaining an analog output signal by adding the outputs of , a code converter that inputs an input code obtained by shifting the digital input signal by a predetermined value to the first and second digital-to-analog converters.

The code converter is.

Of the plurality of bits constituting the input code to the first digital-to-analog converter, only l bits (only I
and a first storage circuit that stores a correction shift amount when a roar occurs.

a digital adder that sequentially digitally adds the corrected shift amounts read from the first storage circuit;

a first selector that selectively takes out either the input code, the previous addition output, or the current addition output from the digital adder;

a latch that latches an output selectively taken out from the first selector and supplies the latch output to the first and mλ digital-to-analog converters as an output of the code converter;

Control is performed to sequentially read correction shift amounts for higher-order bits of the plurality of bits from the first storage circuit, and input the correction shift amount to the first digital-to-analog converter. It is determined whether or not to add the corrected shift amount when only l bits out of the plurality of bits constituting the code become l to the input code, and when performing the addition, K accumulates the corrected shift amount and The present invention is characterized by comprising a sequencer that adds a cumulative output to the input code and controls the added output to be latched in the latch.

The present invention also provides a first digital-to-analog converter that generates an output of the upper digits, and a first digital-to-analog converter that generates an output of the lower digits.
The g-co digital converter generates a full-scale output that is always larger than the output value for 1 bin (/L8B value) of the least significant digital input of the digital-to-analog converter.
with an analog converter.

Adding means for adding the output of the first digital-to-analog converter and the output of the first digital-to-analog converter to obtain an analog output signal.

The input code obtained by shifting the digital input signal by a predetermined value so that the relationship between the digital input signal to the first and first digital-to-analog converters and the analog output signal is approximately linear. and a code converter input to the first digital to analog converter.

The code converter is.

Said I! Of the plurality of bits constituting the input code to the l digital-to-analog converter, only l bits are l
a first storage circuit that stores a corrected shift amount when .

a second storage circuit that stores a correction shift amount caused by a nonlinear error in correspondence with an input code to the first digital-to-analog converter;

Said l! Digital addition/subtraction that sequentially digitally adds/subtracts the corrected shift amount read out from the storage circuit (1) The input code, the previous addition/subtraction output of the digital adder/subtraction device output i, etc., and the current addition/subtraction output (1) II/selector to take out.

a first bus selector for selecting one of the outputs of the first and second storage circuits;

A latch that latches an output selectively taken out from the first selector and supplies the latch output to the first and second digital-to-analog converters as an output of the code converter.

Control is performed to sequentially read correction shift amounts from the correction shift amount for higher-order bits among the plurality of bits from the first generation aspiration circuit, and input the correction shift amount to the first digital-to-analog converter. It is determined whether or not to add or subtract i correction hood amounts such that only l bits out of a plurality of bits constituting the code are l to the input code, and when performing the addition or subtraction, the correction shift amounts are accumulated and a sequencer that controls the cumulative output to be added to or subtracted from the input code, and the added/subtracted output is latched in the latch; The present invention is characterized in that a shift amount due to a non-m-type error is continuously outputted from the memory circuit, and if the shift amount is positive, addition is performed, and if the shift amount is negative, subtraction is performed. How to output l bits of the digital input of the least significant digit in the upper digit part (a digital-to-analog converter that generates a full-scale output in the lower-order part that is always larger than the value of lL8B, and a digital-to-analog converter) A code for inputting an input code obtained by shifting the 1Iff digital input signal by a predetermined value to the original digital-to-analog converter so that the relationship between the digital input signal and the analog output signal is almost linear. In a digital-to-analog converter having a converter.

The code converter is.

a first storage circuit that stores a correction shift amount when only one l bit of a plurality of bits constituting the input code to the upper digit part of the original digital-to-analog converter becomes I;

a digital adder that sequentially digitally adds the corrected shift amounts read from the test tllit storage circuit;

a first receiver for selectively taking out either the input code, the previous addition output, or the current addition output from the digital adder;

Applicable! latching the output selectively taken out from the /7 letter, and using the latch output as the output of the code converter;
and a latch that supplies the original digital-to-analog converter.

Control is performed to sequentially read the corrected shift amount from the first storage circuit starting with the corrected shift amount for the higher-order bits of the plurality of bits, and the input to the upper digit part of the original digital-to-analog converter is performed. Determine whether or not to add the corrected shift amount when only l bits of the plurality of bits constituting the code become I to the input code, and when performing the addition, accumulate the corrected shift amount, and The present invention is characterized by comprising a sequencer that adds an output to the input code and controls the added output to be latched in the latch.

Furthermore, the present invention provides an original digital-to-analog converter that generates a full-scale output in the lower digit part that is always larger than the output value (lLlill value) of l bits of the least significant digit digital input in the upper digit part; The input code obtained by shifting the digital input signal marked * by a predetermined value so that the relationship between the digital input signal and analog output signal for the original digital-to-analog converter is #t[linear] is and a code converter input to the analog converter.

The code converter is.

A first generation circuit that stores a correction shift amount when only l bits of a plurality of bits constituting the input code to the upper digit part of the original digital-to-analog converter become l.

a second storage circuit that stores a correction shift amount due to a nonlinear error difference in correspondence with an input code to a high-order digit portion of the original digital-to-analog converter;

a digital adder/subtracter that sequentially digitally adds/subtracts the corrected shift amount read from the first storage circuit;

a first selector for selectively taking out either the input code, the previous addition/subtraction output, or the current addition/subtraction output from the digital adder/subtractor;

a second path selector that selects one of the outputs of the first and second storage circuits;

a latch that latches an output selectively taken out from the first selector and supplies the latch output to the original digital-to-analog converter as an output of the code converter;

Control is performed to read correction shift amounts sequentially from the first storage circuit starting with correction shift amounts for higher-order bits of the plurality of bits, and the input to the upper digit part of the #epoch digital-to-analog converter is performed. Determine whether or not to add or subtract a correction shift amount when only l bits out of a plurality of bits constituting a code become l to the input code, and when performing the addition/subtraction, accumulate the correction shift amount, and accumulate the correction shift amount. a sequencer that adds or subtracts an output to the input code and controls the addition/subtraction output to be latched in the latch, and the digital adder/subtracter controls the second code converter in response to the code converter output from the latch. The amount of shift due to the nonlinear error is continuously output from the storage circuit, and if the amount of shift is positive, addition is performed.

The feature is that if the value is negative, subtraction is performed.

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram for explaining the principle of code conversion according to the present invention, and shows the ideal characteristics and the original DAO characteristics as well as the shoe F amount switching point.
・So, the shift amount t, oo s Ol, Om , =・
It is shown as... Here, the number of bits of upper DAO is m−
3, the shift amount CM is represented by the decimal number M of the input code, and the co-decimal expansion value corresponding to the shift amount is also shown.
The error On in the characteristics at each carry of the base 0 of the B ax @+l pictogram, which is constructed by connecting the m-bit upper DΔ0 and the m-bit lower low-order 0, is the upper DΔ0 and the lower D
Δ0 and □: The essential error caused by connecting .

This is the sum of the error caused by the load element of the upper DAO.

Corresponding to the code of upper rank 0, if the former of these errors is TM and the latter is IM, a quadratic relationship is obtained.

On = 'I'M +1M (
1) Assuming that the elements DA and O are satisfied on the addition side, the error numerator and IM are as follows.

However, 'I! is the amount of jump in the negative direction when carrying from the lower DAO to the upper DAO &M is the code of the upper DAO 10
This is the value expressed in decimal. p is the number of upper D^0 bits (10
Individual bits when M is expanded into base 1 (base number), that is, 2
Shows the base/decimal conversion value. 1Bp is the sum total when the code by the weight element becomes I when only each bit becomes I.

From equations (2) and (3), equation (1) becomes as follows.

The error Om is the same when the upper DAO codes are equal in one element p^0, and becomes 0!1-0M for the 1M bit shift amount -10M, and further T・co +1B
Since p is the shift amount when only p bits of the upper DAO are l, if this is Op, then equation (4) becomes the following (5)
The formula becomes

On -OH=X Op (5
) - O In other words, since the shift amount On of any input code is the sum of the shift amounts Op of the upper DΔ0 codes of the input code, it is left in Figure 1 as follows, 0l
-01, Q@wmQ Tomi +01 Tomiju 01 +C* y
'4-Tomi04.

0@x04+01, OH-04+OB, 01-
It can be expressed as 04+Os+J.

The tRJ diagram is an enlarged diagram of the vicinity of the switching of the upper D^0 human power in the former DAO, and, like FIG. 1, is a diagram for explaining the present invention in detail. As can be seen from Fig. 2, when the input code is larger than the code at the switching point JM with respect to the input code M, the shift amount O
If you add M to the input code and make it ^0 manual power, you will get the correct analog output. Here, the problem is determining whether the input code is larger or smaller than the code at the switching point JM, but since the shift amount oM can be known in advance, the shift amount OM is added to the input code.

If the value is included in the region of M+/ shown in the second diagram, it can be determined that the input code is larger than the code at the switching point JM.

Therefore, starting from the most significant bit, we sequentially generate the shift amount when only that bit becomes l, and then add the shift amount to the input code to determine whether the value of the relevant digit is l or O. By determining and cumulatively adding the shift amounts when l, the sequential shift amounts can be obtained. Note that when the value of the first corresponding bit is l, the determination can be made without performing addition.

FIG. 1 shows the procedure of ;-code conversion in the present invention based on the above principle. Here, DIN is the input code, not
The wings are converted codes (including the converted codes obtained when the flow in Figure 3 is completed).

m is the number of upper D^0 bits, and OM is the shift amount of the Δth bit. Here, in Figure 1, the ideal analog output when D is input as a digital input is 'I
Calculation of the shift amount will be explained using an example of a case where the deal is set to -. First, a shift amount 04 is added to the digital input. Since the corresponding digit of the upper D^0 at that time, that is, the most significant digit (A-@wm J ), is l, the value D1 obtained by adding 04 to the input code D is set as DQXN. At that time, the corresponding digit of °, that is, the 2nd bit from the top (^-J
-/eco) is l, so the shift amount is set to o4 +O. Similarly, when 01 is added to Dl, the J pick) from the top is O, so the shift amount becomes 04 +Ch, and by adding this shift amount 04 +01 to the input code DK, the converted code DGI) I becomes D get the benefits.

FIG. 1 shows an embodiment of the code converter in the digital-to-analog converter of the present invention, where l is a digital input terminal and c is an analog/4G output terminal.

Reference is a digital adder, and j^ and jB are storage circuits in the form of ROM, etc., with storage capacities koXD (D is the unit correction amount at the switching point of the upper DAC) and mXo (Q is the unit correction amount for each bit), respectively. , t^ and 4B are bus selectors, °7A and 7B are sequencers, t is a latch,
FMU-DEG are control signal lines.

FIG. 5 shows the operation of each part of the circuit shown in the second figure, which is controlled by the sequencers 7A and 71, in correspondence with the states of the two path selectors 6m and 1B. First, in the first step (1), a control signal is supplied from the sequencer 7B to the bus selector 4 via the signal @P0, and its input terminal C is selected.

As a result, in the 0th-order step (2) of latching the input code DIN input to terminal l into the latch r, the path selector B selects the input terminal B, and the ROMjm
1 and transfers the read output to the adder 6B via the input terminal B of the bus selector 6B.

Here, the input cap latched to t = 'do DIN
and add. iLOMjB has a shift amount of 1 when only one bit is input manually, for example, the shift shown in the first diagram *
C1#Ox+04 and the CM of equation (5) are recorded in advance, and controlled by the sequencer 7Δ so that they are read out in order from the higher focus shift amount. Step (
In 3), the sequencer 7 determines whether the content of the digit corresponding to the most significant bit (Δ=mth bit) of the one-dimensional DAo is 1 or 0 as a result of addition. If the result of this addition is l, either the bus selector 6^ or the input terminal^ is selected, and the addition result is transferred to the lunch r and latched. If the result of the addition is O, bus selector tA selects input terminal B, and the input code remains latched in latch l.In step (4), sequencer 7 Todoroki selects the most significant digit. to the next digit (A-^-l) and repeat steps (2) and (3) for that digit. Hereafter, in the same way, step (2), (
5) and (4) are repeated m times, the number of upper bits of the element D^0, and the obtained addition results are latched one after another into latch 1. When this process is completed, move to step (5). Bus selector 4B selects input terminal Todoroki.
ROM j A is driven, and the read result is added to the code obtained by repeating steps (2), (5), and (4). In order to incorporate and correct errors in the case where the S-shaped property is not guaranteed in the 1-element DAO, the ROM j Todoroki has a non-i
The shift amount due to the II type error is memorized and the step (
In step (6), the bus selector 6B selects the input terminal M, and the correction output is transferred to the latch t and latched.

No.! In the illustrated DΔC circuit, adder tei, ROMI
As the bus selectors 1 and 4B, and the ratte t, various commercially available conventional IC elements can be used. The sequencer 7m is 1, for example, the 4th
It can be configured as shown in the figure. here, //
~/l is a chindogut, /9 and X are an and gate,
2/ is an inverter, n is a conventional decimal/n-ary converter, H is a conventional decimal kakunta, and the output of kakunta n is converted into a binary/n-decimal converter.
Supplied to the IO base converter. 3 is R of m@ which supplies the decimal output from the co-decimal-1σ base converter to ROM j B.
The OM drive signal terminal B is an input terminal that receives a signal of m bits of the upper digit part of the addition output (mj bits) from the digital adder. M and B are terminals that connect the bus selector to the select signal to Todoroki.

The select signals of these terminals and 1B are @
Select the input terminal of bus selector 4A at t II and 10°, and similarly select @0" and @/" respectively.
Select the input terminal B of the path selector 4 for Notoe, and send the signal when both terminals BU and IB signals are @O''.
*When the signal of DE0 becomes @l'', the input terminal C of the bus selector 4 is selected. 1 is the input terminal of the path selector 4 and the switching signal input terminal between B and 0, and the switching signal AND gates n and JK are supplied. The decimal output and the signal from terminal B are supplied.The NAND outputs of these NAND outputs from /2 to n are supplied to the multi-input NAND output. , and goo) X is supplied via inverter l.Terminal J
7. Each signal to x and 2 is supplied from a sequencer 7B, which will be described later with respect to the iris 7 diagram.

A lock signal is supplied to the locking tacho via terminal 1 as shown in the gt diagram. The count output obtained thereby is supplied to the 1-/σ-base conversion Wk22.

In response to the 4-way signal, the decimal numbers are sequentially @l
” is obtained. In response to each of the decimal inputs, the ROMjB is driven and the operations of steps Q) to (4) shown in #!1 are repeated. Counting is performed a number of times equal to the number m of the upper Dm0, and when this is exceeded, it is set via terminal I. Corresponding to the upper m bits of the source Dm0 from the adder reference. The addition output and the decimal output are supplied to [Nandogoo) // through each Nandogoo)!2~/l, and if the value of the corresponding bit is °/@ as a result of digital addition, then from Nandogoo) // '''Enable to output 1111.

FIG. 7 shows an example of the configuration of the sequencer 7B, where 3/,
n and n are R8 flip-flops, 3-V are flip-flops with reset, q is an inverter, and Q is an AND gate. Flip-flop J/, N, H,...
, #/ are connected in cascade, and a start signal BT is externally applied to the set input terminal of the first stage flip-flop J.

When the flip-flop evaluation ~#/ and the inverter are affected, the clock signal OLK t J) is supplied from the outside, and the Q output of the flip-flop evaluation is supplied to the terminal 7 as well as to the reset input terminal of the tree prop J/. The Q output of the tree prop 3j is sent to the signal line 0. The Q output of the flip-flop is connected to the flip-flop n and 33
(Cera) input terminal. Q to Tsuritsubprop
The output is supplied to the reset input terminal of the 7-lipfp tube n. The Q output of the tree prop V is supplied to the reset input terminal of this flip q and the reset input terminal of the tree prop n. Tsuritsubprop 32 Q
The output is supplied to the signal line 9D and the AND gate q, and the Q output of the tree prop 33 is supplied to the terminal ffK. The outputs of the inverters are supplied to the AND gate Q, and the output of the AND gate Q is supplied to the terminal l. In addition, Furi 1
The number of flops ~ I is set to m, and when the upper DAO has r bits, it is set to mws f.

As shown in the sequencer 7BK1gtWJK shown in FIG. J and j, and signal line 9C
And DK can obtain a signal as shown in rWA.

As described above, the code converter according to the present invention obtains a digital output of (m+J) bits (m+J) after code correction is performed on the digital input signal DIM K, and this digital output is converted into an individual signal as shown in the figure. It is supplied to the upper digit and lower digit DAO or the upper digit and lower digit parts of one DAO.

Figure 1 is a configuration diagram for explaining the basic principle of the present invention. 1/ is a digital input signal terminal, ! 7 is the analog output signal terminal, and 77 is the upper D that generates the output of the upper digit.
AO (this is MDA (denoted as l), j# is the lower DAO that generates the output of the lower digit (this is denoted as LDAO),!!
is an analog adder,! Haruka is the code converter shown in III-tei.

LDAO! If the full scale of 4I- is made thicker than ΔCl j'J's/L8B, and its linearity is satisfied at the resolution of LDAOj<A, then %LDmuOj4
! From this, a characteristic that decreases during carry in MDAOjJ can be obtained. A jump in the negative direction occurs at a point where a carry occurs from LDAOj4c to MDAO11, and the characteristic curve of LDAOj4c is superimposed from that point as a starting point. Now convert your digital input to code! 4), properties satisfying the II form property can be obtained.

FIG. 70 shows a specific embodiment of the above-mentioned l[)AOII and LDAOj, where ti is a digital input signal terminal, 4J is an analog output signal terminal, and 63 is a reference voltage vr@f terminal '5LOe'. 1. l+ −”−
・e'Lj-1;'MO+'Ml e'-'-1
”MW-1 is an analog switch, 0.0°CLO*O
LI + -”' * 0LI-1 also has O capacity on the lower digit side.
M・-'M 1 e・・・・e CMl! l-1 is the capacitance on the upper digit side. A capacitor array 0° arranged in a binary weighted manner corresponding to the digital input pitch F. *
The outputs of the m-bit LDAOj from OL□ to OL-1 and the similarly connected m-bit MDAOjJ are mutually coupled by a capacitor Oc. In this circuit, the value of the coupling capacitance is 0°.

The capacitor string of LDAOj on the LgB side from the right terminal operates as a normal DA0 with m-bit resolution.

This is LDAO14! The output of the coupling capacitance is 0. Yosuh
This is because the output of MDAOJrJ is multiplied and added to the output of MDAOJrJ, and the analog addition of the output of MDAOZS and the output of LDAOiu is realized by the coupling capacitance of 0°, so the value of this capacitance of 0° is the value of the LDAOj reference. The slope of the input pair is larger than ideal, and even if the error caused by MDAO13 is considered, if the coupling capacitance Oc is set appropriately, the LD will always be
Mu0! If you set it appropriately larger than 1iO0] for the carry from Tate to Yudoro 013, LDAOj and MDAOs
There will be no square or identical jump at the output junction with 3. LDΔOj4'O non-fermented error is 3A with a resolution of 21
Keep it within L8B and set the value of Yada CC to cover MDAO13's false retainer and finish 4.

There is a level in the analog output at which linearity corresponding to /LSB of LDΔOj≠ is maintained, and by changing the digital input to the digital input of the original DAC that can obtain linearity, linearity can be achieved. power i satisfied D
A(3 is obtained.

FIG. 11 shows an example in which 1) a DA converter is constructed by a series of capacitor strings without configuring a Δ converter in a form divided into upper and lower parts as shown in FIG. Here, the analog switch SLO+ 8L1t..."s 8Lj-1.

8MOe SMl + """ + 8MIfl-1 is controlled in the same way as in the y and iu diagrams to perform successive approximation.

Capacity coo + CLl +...

CLj-1; OMO+ CMl +・・−・・・・+
As shown in the clUn-1k construction diagram.

/, /C, /, 10.220. respectively.・・・－・・・
, (/, IXλ)0゜2'Oa -2""01"
"-e 2"'-"O constant melody. Capacity 0°.

The lower digit part of ~0LI-1 corresponds to lower D^ conversion wIK.

Its full scale is 1 for example! -3 when (r, ro
7t2tta) vr, 1tea t), the capacitance OM・~0. l step at −8, e.g. (10/l at mxx g)
By using the Otori converter of this example, which is set to be larger than Vr@t, in place of the MDAO 13 and LDAOsa shown in the second diagram, a similar DA converter can be constructed.

As explained above, according to the present invention, the storage capacity of the storage circuit can be significantly reduced. That is, the storage capacity of the storage circuit according to the present invention is (number of bits of upper DA0) x (number of bits representing the shift amount), assuming that there is no one-dimensional DAOK nonlinear error and the adder is completely satisfied. On the other hand, when storing all switching points and shift amounts in accordance with the resolution of the upper DΔ0, the storage capacity of the memory circuit is (resolution of the upper DΔ0) x (shift (number of bits representing the amount) ) + (resolution of high order 0) x (number of bits representing 9 switched points) It can be seen that the storage capacity is significantly reduced by the present invention.

If the adder is not satisfied, (number of bits of upper DAO) × (number of bits representing the shift amount of each bit) + (resolution of upper D^0) × (number of bits representing the shift amount for nonlinear error) ). Most of the shift amount for any given code is due to the "jump".

The difference due to non-iI type difference is very small.If the jump of S7 times is 1018B and the number of bits of upper DAO is t bits, the maximum jump amount is coj4 X t L8B, that is, l/bit. On the other hand, the nonlinear error is 3~!
It can be reduced to about a bit. Therefore, the degree of improvement is large in this case as well.

Regarding the conversion speed, in the present invention, it is only necessary to access the memory circuit several times for bits of the upper DAO, and perform processing such as addition on the successive outputs, and all switching points and In the case of storing the shift amount '1', compared to the case of accessing a memory circuit that stores N number of switching points corresponding to the resolution of the upper DAO and comparing the readout output with the input code. , the conversion speed can be significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a characteristic diagram showing an example of the characteristics of the upper 3 bits [R1] for explaining the principle of code conversion according to the present invention.
1 is a partially enlarged view of FIG. 1, FIG. 3 is a diagram for explaining the procedure of code conversion according to the present invention, and FIG. 1 is a diagram showing an example of the code converter according to the present invention. figure,#! Figure J is an explanatory diagram of the operation sequencer of the code converter shown in the first diagram, Figure R4 and Figure 7 are circuit diagrams showing specific examples of the λ sequencer shown in the first diagram, and Figure 1 is the diagram shown in Figure 1 and Figure 7. Figure 9 is a timing chart for explaining the operation of the sequencer of the present invention.
FIG. 2 is a circuit diagram showing an example. l...Digital input terminal. Core: Analog 4G output terminal, 4I--Digital adder. ! Δ, H3-E memory circuit, Todoroki, AB...path selector. 7^, 7B...Sequencer, t...Latch. ? Δ~deG...Control signal line, //-/r...Nant gate. /9. x...ant'l-), 2/...inverter, n...-adic/lσ-adic converter, 2F...Kakunta. S...iLOM drive signal terminal, 2t...addition input terminal. Mumu, MuB - Select signal output terminal. l...Switching signal input terminal, l...Clock input terminal. , V-...Reset input terminal. J/, n, J3-R8y lip flop Q7p. Review~l/...D flip-flop with reset. ξ・−invar! , q...and gate. zi・-Digital input signal terminal. ! -Analog output signal terminal. j3... Upper DAO, j4'... Lower DOM0゜j!
... Analog adder! ≦・・・Code converter,
4/-...Digital input signal terminal. 4 terminals: Analog output signal terminals. 4J...Reference voltage terminal. 8L・l5Lle -l8LJ-1: SM<Is S
Ml + ”' + '1lffl-1°°° Analog switch. '06 e at, o I OLI + ”' * 0
Lj-1; OMO+ OMI + '-' * 0M
In-1... Capacity. 0゜・・・Coupling capacity. Patent applicant Nippon Telegraph and Telephone Corporation

Claims (1)

[Scope of Claims] 1) A first digital-to-analog converter that generates an output of the upper digit, and l bits of the digital input of the least significant digit of the l-th digital-to-analog converter as an output of the lower digit. a second digital-to-analog converter that generates a full-scale output that is always larger than the output value (/LaB value); an adding means for adding the output signals to obtain an analog output signal; In a digital-to-analog converter, the code converter inputs an input signal obtained by shifting an input signal by a predetermined value to first and second digital-to-analog converters. The code converter includes an @1 storage circuit that stores a correction shift value when only l bits of the plurality of bits constituting the input code to the first digital analog converter become l. . a digital adder for sequentially digitally adding correction shift amounts read from the first storage circuit; a first selector that selectively takes out either the input code, the previous addition output, or the current addition output from the digital adder; Latching the output selectively taken out from the first selector, and using the latch output as the output of the code converter,
Said I and first digital-to-analog conversion 1) K
With latch to supply. Control is performed to sequentially read correction shift amounts from the first storage circuit starting with correction shift amounts for higher-order bits among the plurality of bits. Determine whether or not to add to the input code a correction shift amount when only l bits of the plurality of bits constituting the input code to the first digital-to-analog converter are l, and perform the addition. When performing, the correction shift amount is accumulated and the accumulated output is added to the input code,
A sequencer for controlling the addition output to be latched in the latch.
analog converter. 2) ``A first digital-to-analog converter that generates the output of the most significant digit, and a digital input of the least significant digit of the first digital-to-analog converter as the output of the least significant digit! a first digital-to-analog converter that generates a full-scale output that is always larger than the output value for pits (the value of z18B); and converting the output of the first digital-to-analog converter and the second digital-to-analog converter. an adding means for obtaining an analog output signal by adding the outputs of the converters, and the relationship between the digital input signals to the first and second digital-to-analog converters and the analog output signal is approximately linear. , a code converter that inputs an input code obtained by shifting the digital input signal by a predetermined value to the first and second digital-to-analeg converters. The above-mentioned; - code converter is. a first storage circuit that stores a correction shift amount when only l bits of a plurality of bits constituting the input code to the first digital-to-analog converter become l; Non-IIyi! corresponding to the input code to the digital-to-analog converter of the turtle I゛! a second storage circuit that stores a correction shift amount caused by the p error; and a digital addition/subtraction circuit that sequentially digitally adds and subtracts the correction shift amount read from the first storage circuit. a first selector for selectively taking out either the input code, the previous addition/subtraction output, or the current addition/subtraction output from the digital adder/subtractor; and a second copass selector that selects one of the @/ and the output of the second storage circuit. a latch that doubles the output selectively taken out from the first selector and supplies the latch output to the first and second digital-to-analeg converters as the output of the code converter; Control is performed to read correction shift amounts sequentially from the correction shift amounts for higher-order bits among the plurality of bits from one storage circuit. Determine whether or not to add or subtract a correction shift amount to the input code when only l bits of the plurality of bits constituting the input code to the l-th digital-to-analeg converter become l, and When performing addition and subtraction, K is equipped with a sequencer that controls to accumulate the correction shift amount, add and subtract the accumulated output to the input code, and latch the addition/subtraction calculation output in the latch. The digital adder/subtractor responds to the code converter output from the latch, continuously outputs a shift amount due to a nonlinear error from the second storage circuit described in CI, and performs addition if the shift amount is positive. A digital to analog converter that performs subtraction. 3) I of the digital input of the least significant digit in the upper digit part.
An original digital converter that generates a full-scale output of the lower digits that is always larger than the output value for bits (the value of tL8B).
with an analog converter. The input code obtained by shifting the digital input signal marked * by a predetermined value is converted into the original digital-to-analog converter so that the relationship between the digital input signal and the analog output signal to the original digital-to-analog converter is almost linear. In a digital-to-analog converter having a code converter input to the converter. The code converter is. a first storage circuit that stores a correction shift amount when only l bits of the plurality of bits forming the input code to the upper digit part of the original digital-to-analog converter are inverted; a digital adder that sequentially digitally adds the corrected shift amounts read from the first storage circuit; a first selector that selectively takes out either the input code, the previous addition output, or the current addition output from the digital adder; a latch that latches the output selectively taken out from the first receiver and supplies the latch output to the original digital-to-analog converter as an output of the code converter; Control is performed to sequentially read correction shift amounts from the first storage circuit starting with correction shift amounts for higher-order bits among the plurality of bits. Determine whether or not to add to the input code a correction shift amount when only l bits of a plurality of bits constituting the input code to the upper digit part of the original digital-to-analog converter become l, and A digital-to-analog converter comprising: a sequencer that accumulates the corrected shift amount when performing addition, adds the accumulated output to the input code, and controls the added output to be latch-latched. . 4) I of the digital input of the least significant digit in the upper digit part
An original digital converter that generates a full-scale output for the lower digits that is always larger than the output value for the PIF (value of tL8B).
with an analog converter. The input code obtained by shifting the digital input signal by a predetermined value is converted into the original digital-to-analog converter so that the relationship between the digital input signal and the analog output signal to the original digital-to-analog converter is approximately 1i. In a digital-to-analog converter having a code converter input to the converter. The code converter is. a first storage circuit for storing a correction shift (quantity) when only l bits of a plurality of bits constituting the input code to the upper digit part of the original digital-to-analog converter become l; a second storage circuit that stores a correction shift amount caused by a nonlinear error in correspondence with an input code to a high-order digit portion of the analog converter; and sequentially digitally adds and subtracts the correction shift amount read from the vote storage circuit. a digital adder/subtractor; an II/selector for selectively taking out either the previous addition/subtraction output or the current addition/subtraction output from the human board and the digital adder/subtractor; one of the outputs of the first and first storage circuits; a second bus selector for selecting; and a latch for latching the output selectively taken out from the 1sl selector and supplying the latch output to the m-era digital-to-analog converter as the output of the code converter. Control is performed to sequentially read out correction shift amounts for higher-order bits of the plurality of bits from a first storage circuit, starting with the correction shift amount of [. It is determined whether or not to add or subtract the corrected shift amount when only l bits out of the plurality of bits constituting the code are I to the input code, and when performing the addition/subtraction, the corrected shift amount is accumulated, and the accumulated a sequencer that adds and subtracts the output to the input code and controls the addition/subtraction output to be latched to the latch; A digital-to-analog converter characterized in that a shift amount due to a nonlinear error is read out from , and if the shift amount is positive, addition is performed, and if the shift amount is negative, subtraction is performed.