JPS6326927B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a digital-to-analog converter that has high resolution but does not satisfy accuracy, that is, does not satisfy linearity.
A digital-to-analog converter (abbreviated as DAC) that performs so-called digital trimming to correct linearity and improve accuracy.
This invention relates to a digital-to-analog converter (abbreviated as DAC), and in particular to a digital-to-analog converter whose input code converter has been improved to increase the conversion speed and reduce the size of the memory circuit.

The present inventors applied digital trimming to
As a DAC, Japanese Patent Application No. 127239 (1982)
53144), the first digital-to-analog converter (upper digit
DAC) and a first digital-to-analog converter (abbreviated as lower DAC) as the output of the lower digit.
a second digital-to-analog converter that generates a full-scale output that is always larger than the output value of one bit (1LSB value) of the digital input of the least significant digit; an addition means for obtaining an analog output signal by adding the outputs of the two digital-to-analog converters, and a relationship between the digital input signal and the analog output signal for the first and second digital-to-analog converters is approximately linear; We have proposed a digital-to-analog converter equipped with a code converter that inputs an input code obtained by shifting a digital input signal by a predetermined value to the first and second digital-to-analog converters so that the digital input signal is shifted by a predetermined value.

Here, the upper DAC and lower DAC can be composed of the original DAC, and an example of the 3-bit characteristics of the upper DAC is shown in Figure 1.
The output change at the carry point of the input to the DAC is always reduced. In order to correct this characteristic to the ideal characteristic shown in FIG. 1, it is necessary to perform the following code conversion. In other words, in Figure 1, adding a certain value to the digital input value to move the input/output characteristics of the digital-to-analog converter on the digital input axis (X-axis) is called a shift, and this certain value is called the shift amount. In other words, when the input codes at the positions where the correction amount switches are J ₀ , J ₁ , J ₂ , etc., when the input code is 0 to J ₀ , the shift amount C ₀ (=0 ), C ₁ when J ₀ to J ₁ , etc., it is necessary to determine the correction amount from the input code and add the correction amount corresponding to the input code to the input code.

In that case, input codes J ₀ ~ J ₁ , J ₁ ~ _{J 2} , ...
The problem is to identify in which region it is located. In principle, the input code is successively compared with the switching point codes J ₀ , J ₁ , J ₂ , ..., J _o , the code J _q for which the input code is larger is found, and the input code is in the area. It can be identified that it is between J _q-1 and J _q . However, in the worst case, the number of comparison operations will be equal to the number of switching points J _o , that is, the number of times corresponding to the resolution of the upper DAC, and the above-mentioned DAC has the disadvantage of requiring a long processing time. be. Furthermore, the basic comparison operation can be realized by reading data indicating the switching point from the memory circuit, taking the two's complement of that data, and adding it to the input code; however, access to the memory circuit, The read data is inverted and added twice, which further increases the processing time. The above is a major hindrance to shortening the DA conversion time of the DAC proposed above. In addition, the configuration of the logic circuit to perform this kind of processing also becomes complex.
In particular, there was also the problem that the storage capacity of the storage circuit became large.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned problems, to make it possible to immediately determine the switching point from a digital signal of a part of the input code, to increase the DA conversion speed, and to reduce the size of the memory circuit. An object of the present invention is to provide a digital-to-analog converter that is small in size.

To achieve such an object, the present invention provides a first digital-to-analog converter that generates an output of the most significant digit, and a digital input of the least significant digit of the first digital-to-analog converter as an output of the least significant digit. a second digital-to-analog converter that generates a full-scale output that is always larger than the output value of 1 bit (1LSB value); an adding means for adding the outputs of the converter to obtain an analog output signal;
An input code obtained by shifting the digital input signal by a predetermined value is applied to the first and second digital-to-analog converters so that the relationship between the digital input signal to the digital-to-analog converter and the analog output signal is approximately linear. and a code converter input to the digital-to-analog converter, the code converter converting one of the plurality of bits constituting the input code to the first digital-to-analog converter. a first memory circuit that stores a corrected shift amount when only the bit becomes 1; a digital adder that sequentially digitally adds the corrected shift amount read from the first memory circuit; and the input code and the digital adder. a first selector that selectively takes out either the previous addition output or the current addition output from the code converter; and a first selector that latches the output selectively taken out from the first selector, and sends the latch output to the code converter. a latch that supplies the output to the first and second digital-to-analog converters; and a latch that supplies the first and second digital-to-analog converters with the corrected shift amount sequentially from the first storage circuit starting with the corrected shift amount for the higher-order bits among the plurality of bits. control so that only one bit of the plurality of bits constituting the input code to the first digital-to-analog converter is 1.
It is determined whether or not to add the corrected shift amount when it becomes The present invention is characterized by comprising a sequencer that controls the latch to latch.

Further, the present invention provides a first
a digital-to-analog converter, and generates a full-scale output that is always larger than the output value of 1 bit (value of 1 LSB) of the digital input of the least significant digit of the first digital-to-analog converter as the output of the lower digit. a second digital-to-analog converter; addition means for adding the output of the first digital-to-analog converter and the output of the second digital-to-analog converter to obtain an analog output signal; and such that the relationship between the digital input signal to the second digital-to-analog converter and the analog output signal is approximately linear;
a code converter that inputs an input code obtained by shifting the digital input signal by a predetermined value to the first and second digital-to-analog converters, the code converter comprising: a first storage circuit that stores a correction shift amount when only one bit of a plurality of bits constituting the input code to the first digital-to-analog converter becomes 1; and the first digital-to-analog converter; a second storage circuit that stores a correction shift amount caused by a nonlinear error in accordance with an input code to the converter; a digital adder/subtractor that sequentially digitally adds and subtracts the correction shift amount read from the first storage circuit; a first selector for selectively taking out either the input code, the previous addition/subtraction output and the current addition/subtraction output from the digital adder/subtractor; and a second bus for selecting one of the outputs of the first and second storage circuits. a selector; a latch that latches the output selectively taken out from the first selector and supplies the latch output to the first and second digital-to-analog converters as the output of the code converter; Control is performed to sequentially read correction shift amounts from the first storage circuit starting with correction shift amounts for higher-order bits among the plurality of bits, and the input code to the first digital-to-analog converter is Only one bit out of the multiple bits that constitutes is 1
It is determined whether or not to add or subtract the corrected shift amount when the above input code is obtained. When performing the addition/subtraction, the corrected shift amount is accumulated, the cumulative output is added or subtracted from the input code, and the output of the addition/subtraction is added to or subtracted from the input code. and a sequencer for controlling the latch to latch, and the digital adder/subtracter reads the shift amount due to the nonlinear error from the second storage circuit in response to the code converter output from the latch, and It is characterized in that addition is performed if it is positive, and subtraction is performed if it is negative.

Furthermore, the present invention provides an original digital-to-analog converter that generates a full-scale output in the lower digit part that is always larger than the output of one bit (value of 1 LSB) of the least significant digit digital input in the upper digit part; The input code obtained by shifting the digital input signal by a predetermined value is sent to the original digital-to-analog converter so that the relationship between the digital input signal and the analog output signal to the original digital-to-analog converter is almost linear. In a digital-to-analog converter having a code converter for input, the code converter is configured such that only one bit of a plurality of bits constituting the input code to the upper digit part of the original digital-to-analog converter is 1. a first storage circuit that stores the corrected shift amount when , a digital adder that sequentially digitally adds the corrected shift amount read from the first storage circuit, and the input code and the previous value from the digital adder. a first selector that selectively takes out either the addition output of or the current addition output, latches the output selectively taken out from the first selector, and uses the latch output as the output of the code converter; a latch for supplying the original digital-to-analog converter; and a latch that supplies the original digital-to-analog converter; Determine whether or not to add to the input code a correction shift amount when only one bit of the plurality of bits constituting the input code to the upper digit part of the digital-to-analog converter is 1, and perform the addition. The present invention is characterized in that it comprises a sequencer that controls to accumulate the corrected shift amount, add the accumulated output to the input code, and latch the added output in the latch.

Furthermore, the present invention provides an original digital-to-analog converter that generates a full-scale output in the lower digit part that is always larger than the output value (1LSB value) of one bit of the least significant digit digital input in the upper digit part; The input code obtained by shifting the digital input signal by a predetermined value is transferred to the original digital-to-analog converter so that the relationship between the digital input signal and the analog output signal for the original digital-to-analog converter is approximately linear. A digital-to-analog converter having a code converter for inputting the code to the source digital-to-analog converter, wherein the code converter is configured such that only one bit of the plurality of bits constituting the input code to the upper digit part of the original digital-to-analog converter is input to the code converter. a first storage circuit that stores a correction shift amount when the value becomes 1; and a second storage circuit that stores a correction shift amount caused by a nonlinear error corresponding to the input code to the upper digit part of the original digital-to-analog converter. a circuit; a digital adder/subtracter that sequentially digitally adds/subtracts the corrected shift amount read from the first storage circuit; and selecting either the input code, the previous addition/subtraction output, or the current addition/subtraction output from the digital adder/subtractor. a first selector that selects one of the outputs of the first and second memory circuits; a second bus selector that latches the output selectively taken out from the first selector; A latch supplies the output of the code converter to the original digital-to-analog converter, and sequentially reads the correction shift amount from the first storage circuit starting with the correction shift amount for the higher-order bit of the plurality of bits. control so as to output the input code, and add or subtract from the input code a correction shift amount when only one bit of the plurality of bits constituting the input code to the upper digit part of the original digital-to-analog converter becomes 1. and a sequencer for controlling such that when performing the addition or subtraction, the corrected shift amount is accumulated, the accumulated output is added or subtracted from the input code, and the output of the addition/subtraction calculation is latched in the latch; The digital adder/subtractor reads the shift amount due to the nonlinear error from the second storage circuit in response to the code converter output from the latch, and performs addition if the shift amount is positive;
The feature is that if the value is negative, subtraction is performed.

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram for explaining the principle of code conversion according to the present invention, and shows ideal characteristics and original DAC characteristics as well as shift amount switching points J ₀ , J ₁ , J ₂ , . . .
The shift amounts are shown as C ₀ , C ₁ , C ₂ , . . . Here, the number of bits of the upper DAC is assumed to be m=3, and the decimal number M of the input code and the binary expanded value corresponding to the decimal number of the input code are also shown. The error Co in the characteristics at each carry of an n = m + l bit original DAC configured by connecting an m-bit upper DAC and an l-bit lower DAC _is an error caused by connecting the upper DAC and the lower DAC. min and upper DAC
This is the sum of the error due to the load element. top
Corresponding to the DAC code, if the former of these errors is T _M and the latter is _EM , the following relationship is obtained.

C _o =T _M +E _M (1) Assuming that the original DAC satisfies the addition rule,
The error portions T _M and E _M are as follows.

T _M = T・M=T・( _* 〓 ^p=0 2 ^p-1 ) (2) E _M = ( _* 〓 ^p=0 EBp) (3) However, T is the carry from the lower DAC to the upper DAC The amount of jump in the negative direction of time, M, is the value expressed in decimal form of the code of the upper DAC. p indicates the order of individual bits when the number of bits (decimal number) M of the upper DAC is expanded in binary, _* 〓 ^p=0 2 ^p-1 is the sum of codes that become 1, that is, binary/decimal Indicates the conversion value. EBp
indicates the error due to the loading element when only each bit becomes 1, _* 〓 ^p=0 EBp is 2 corresponding to M
This is the sum when the code in decimal notation is 1.

From equations (2) and (3), equation (1) becomes as follows.

C _o = T・( _* 〓 ^p=0 2 ^p-1 ) + _* 〓 ^p=0 EBp = _* 〓 ^p=0 {T・2 ^p-1 +EBp} (4) The error C _o is the upper When the DAC codes are equal, they are the same, and for the shift amount C _M of the Mth bit, C _o = C _M , and furthermore, T・2 ^p-1 +
Since EBp is the shift amount when only p bits of the upper DAC are 1, if this is set as _Cp , then equation (4) becomes the following equation (5).

C _o = C _M = _* 〓 ^p=0 C _p (5) In other words, the shift amount C _o of any input code is the shift amount of the upper DAC of the input code.
Since it is the sum of C _p , as shown in Figure 1, C ₁
= C ₁ , C ₂ = C ₂ , C ₃ = C ₁ + C ₂ , C ₄ = C ₄ , C ₅ = C ₄ +
It can be expressed as C ₁ , C ₆ =C ₄ +C ₂ , C ₇ =C ₄ +C ₂ +C ₁ .

FIG. 2 is an enlarged view of the vicinity of switching of the upper DAC input in the original DAC, and is a diagram for explaining the principle of the present invention similarly to FIG. 1. As can be seen from Figure 2, for input code M, the switching point
When the input code is larger than the code at the switching point _JM , a correct analog output can be obtained by adding the shift amount _CM to _the input code and making it the original DAC input. Here, the problem is determining whether the input code is larger or smaller than the code at the switching point J _M , but since the shift amount C _M can be known in advance, the shift amount C _M is added to the input code. , if the value is included in the region M+1 shown in the second figure, it can be determined that the input code is greater than the code at the switching point _JM .

Therefore, starting from the most significant bit, the shift amount when only that bit becomes 1 is generated sequentially, and the shift amount is added to the input code to determine whether the value of the relevant digit of the value obtained is 1 or 0. The shift amount can be determined by determining and cumulatively adding the shift amount when the value is 1. Note that when the value of the first corresponding bit is 1, the determination can be made without addition.

FIG. 3 shows the code conversion procedure according to the present invention based on the above principle. Here, D _IN is the input code, D _GIN is the converted code (including the converted code obtained when the flow in Figure 3 is completed),
m represents the number of bits of the upper DAC, and C _M represents the shift amount of the A-th bit. Here, in FIG. 1, calculation of the shift amount will be explained by taking as an example a case where A _ideal is an ideal analog output when D is input as a digital input. First, the shift amount _C4 is added to the digital input D. At that time, the corresponding digit of the upper DAC, that is, the most significant digit (A=m=3), is 1 as shown in Figure 1, so the value D ₁ obtained by adding C ₄ to the input code D is D _GIN shall be. Next, the shift amount C ₂ is obtained as D _GIN . The corresponding digit of D ₂ , that is, the second bit from the top (A=3-1=2), is the first
As is clear from the figure, since it is 1, D _GIN further adds the shift amount C ₂ to become D _GIN +C ₄ +C ₂ . Let the shift amount be C ₄ +C ₂ . Similarly D _GIN , i.e.
When C ₁ is added to D ₂ , the third bit from the top is 0, so the shift amount is C ₄ without adding C ₁ .
+C ₂ remains, and this shift amount C ₄ +C ₂ is added to the input code D to create the converted code D _GIN .
Get _D2 .

FIG. 4 shows an embodiment of the code converter in the digital-to-analog converter of the present invention, where 1
is the digital input terminal, 2 is the analog output terminal,
4 is a digital adder, 5A and 5B have a storage capacity of 2 ^m × D (D is the number of bits that can express the unit correction amount at the switching point of the upper DAC) and m ×
6A and 6B are bus selectors, 7A and 7B are sequencers, 8 is a latch, and 9A to 9G are control signals. It is a line.

FIG. 5 shows the operation of each part of the circuit shown in FIG. 4 controlled by the sequencers 7A and 7B in correspondence with the states of the two bus selectors 6A and 6B. First, in the first step (1), a control signal is supplied from the sequencer 7B to the bus selector 6A via the signal line 9C, and its input terminal C is selected.
As a result, the input code input from terminal 1
Latch D _IN to latch 8. In the next step (2), the bus selector 6B selects the input terminal B, drives the ROM 5B, and transfers the read output to the adder 4 via the input terminal B of the bus selector 6B, where the latch is activated. Add it to the input code D _IN latched at 8. The ROM 5B stores in advance the shift amounts when only individual bits are input, such as the shift amounts C ₁ , C ₂ , C ₄ shown in the first diagram, and _CM of equation (5). Sequencer 7A
Control is performed so that the bits are read out in order starting from the shift amount of the higher order bits. In step (3), the sequencer 7A determines whether the content of the digit corresponding to the most significant bit of the original DAC (A=mth bit) is 1 or 0 as a result of the addition. The result of such addition is 1
If so, the bus selector 6A selects the input terminal A, and the addition result is transferred to the latch 8 and latched. If the result of the addition is 0, the bus selector 6A selects the input terminal B, and the input code remains latched in the latch 8. In step (4), the sequencer 7A instructs to move from the most significant digit to the next digit (A=A).
-1), repeat steps (2) and (3) for that digit. Following steps (2), (3) and (4) in the same manner.
is repeated m times for the upper bits of the original DAC, and the obtained addition results are successively latched into the latch 8. When this process is completed, the process moves to step (5), the bus selector 6B selects the input terminal A, the ROM 5A is driven, and the read result is repeated in steps (2), (3), and (4). Add to the code obtained in . In ROM5A, in order to be able to incorporate and correct errors even when linearity is not guaranteed in the original DAC, there are
The amount of shift due to the nonlinear error at that time is stored and corrected by adding it as described above in the process of step (5). In step (6), the bus selector 6B selects the input terminal A, and the corrected output is transferred to the latch 8 and latched.

In the DAC circuit shown in FIG.
As the ROMs 5A and 5B, bus selectors 6A and 6B, and latch 8, various commercially available conventional IC elements can be used. The sequencer 7A can be configured as shown in FIG. 6, for example. Here, 11 to 18 are NAND gates, 19 and 20 are AND gates, 21 is an inverter, 22 is a conventional binary/decimal converter, and 2
3 is a conventional binary counter, and supplies the output of the counter 23 to a binary/decimal converter 22. 24 is
m ROM drive signal terminals supplying the decimal output from the binary/decimal converter 22 to the ROM 5B; 25 is a signal of m bits of the upper digit part of the addition output (m+l bits) from the digital adder 4; This is an input terminal that receives . 26A and 26B are select signal output terminals to the bus selector 6A, and when the select signals of these terminals 26A and 26B are "1" and "0", respectively, input terminal A of the bus selector 6A is selected, and similarly, each When "0" and "1", input terminal B of bus selector 6A is selected, and both terminals 26A and 26B are selected.
The input terminal C of the bus selector 6A is selected when the signal on the signal line 9C becomes "1" when both signals are "0". 27 is a switching signal input terminal for the input terminals A, B, and C of the bus selector 6A, and the switching signal is input to the AND gates 19 and 20.
supply to. 28 is a clock input terminal for the counter 12, and 29 is a reset input terminal for the counter 12. The NAND gates 12 to 18 are supplied with a decimal output from a binary/decimal converter 22 and a signal from a terminal 25. These nand gates 12-1
8 NAND outputs are supplied to a multi-input NAND gate 11, the NAND outputs are supplied directly to an AND gate 19, and to an AND gate 20 via an inverter 21. Terminals 27, 28 and 2
Each signal to 9 is supplied from a sequencer 7B, which will be described later with reference to FIG.

A clock signal as shown in FIG. 8 is supplied to the counter 23 via a terminal 28. The counter output thus obtained is supplied to a binary/decimal converter 22 to obtain m decimal outputs which are sequentially output from the largest value in response to the clock signal. In response to each 10 output, the ROM 5B is driven and the operations of steps (2) to (4) shown in FIG. 5 are repeated. The count of the counter 23 is equal to the number m of bits of the upper DAC.
is performed a number of times equal to , and after that, terminal 2
9. The element from adder 4
The addition output corresponding to the upper m bits of the DAC and the decimal output are supplied to the NAND gate 11 via each NAND gate 12 to 18, and the digital addition result is
If the value of the corresponding bit is "1", the NAND gate 11 outputs "1".

FIG. 7 shows an example of the configuration of the sequencer 7B, where 31, 32 and 33 are RS flip-flops,
34 to 41 are D flip-flops with reset, 4
2 is an inverter, and 43 is an AND gate. Flip-flops 31, 34, 35,..., 40, 4
1 are connected in cascade, and a start signal ST is externally applied to the set input terminal of the first stage flip-flop 31. A clock signal CLK is applied to flip-flops 34 to 41 and an inverter 42 from the outside.
The Q output of flip-flop 34 is provided to terminal 29 as well as to the reset input terminal of flip-flop 31. The Q output of flip-flop 35 is sent to signal line 9C. flipflop 3
6 is applied to the set input terminals of flip-flops 32 and 33. flipflop 4
A Q output of 0 is provided to the reset input terminal of flip-flop 32. The Q output of flip-flop 41 is applied to the reset input terminal of flip-flop 41 and to the reset input terminal of flip-flop 33. The Q output of flip-flop 32 is supplied to signal line 9D and AND gate 43, and the Q output of flip-flop 33 is supplied to terminal 27. The output of the inverter 42 is supplied to the AND gate 43, and the output of the AND gate 43 is connected to the terminal 28.
supply to. In addition, flip-flops 36 to 39
The number of DACs is m, and when the upper DAC is 8 bits, m=8.

By supplying the clock signal CLK and start signal ST as shown in FIG. 8 to the sequencer 7B shown in FIG.
Signals as shown in FIG. 8 are obtained on signal lines 9C and 9D.

As described above, the code converter of the present invention obtains a (m+l)-bit digital output obtained by performing code correction on the digital input signal _DIN , and converts this digital output into individual signals as shown in FIG. Upper digit and lower digit DAC or one
Supplies the upper and lower digits of the DAC.

FIG. 9 is a configuration diagram for explaining the basic principle of the present invention, in which 51 is a digital input signal terminal;
2 is an analog output signal terminal, 53 is an upper DAC that generates the output of the upper digits (this is referred to as MDAC), 5
4 is the lower DAC that generates the output of the lower digit (this
55 is an analog adder, and 56 is a code converter shown in FIG.

The full scale of LDAC54 is the same as that of MDAC53.
If it is larger than 1LSB and the linearity is satisfied in the resolution of LDAC54, from LDAC54
A characteristic that decreases at the time of carry in MDAC53 is obtained. A jump in the negative direction occurs at the point where carry occurs from the LDAC 54 to the MDAC 53, and the characteristic curve of the LDAC 54 is superimposed with that point as the starting point. Here, by shifting the digital input by the code converter 56, characteristics satisfying linearity can be obtained.

Figure 10 shows the MDAC53 and LDAC described above.
54, 61 is a digital input signal terminal, 62 is an analog output signal terminal, 63 is a reference voltage V _ref terminal, S _L0 , S _L1 , . . .
..., S _Ll-1 ; S _M0 , S _M1 , ..., S _Mn-1 is an analog switch, C ₀₀ , C _L0 , C _L1 , ..., C _Ll-1 is the lower digit side capacitance, C _M0 , C _M1 , ..., C _Mn-1 is the capacitance on the upper digit side. Capacitor arrays C ₀₀ , C _L0 ~ arranged in a binary weighted manner corresponding to the digital input bits.
The outputs of the l-bit LDAC 54 based on C _Ll-1 and the m-bit MDAC 53 connected in the same way are coupled together by a capacitor C _c . In this circuit, the value of the coupling capacitance C _c is changed from the right terminal to the LSB side.
If the capacitance value including the capacitance string of LDAC54 is equivalent to unit capacitance, that is, C _c = 2 ^l / 2 ^l −1 × [unit capacitance], then it is considered as a normal DAC with l + m bit resolution. Operate. This means that the output of LDAC54 is multiplied by 1/2 ^l by the coupling capacitor C _c and
This is because it is added to the output of MDAC53.
Analog addition of the output of the LDAC 54 and the output of the LDAC 54 is realized by a coupling capacitor C _c , and therefore the value of this capacitor C _c determines the slope of the input-to-output characteristic of the LDAC 54 . In other words, if the capacitance C _c is larger than 2 ^l / 2 ^l −1 × [unit capacitance C _p ], the slope will be larger than ideal, and even if the error caused by the MDAC53 is considered, the coupling capacitance C _c must be set appropriately. If, always
Changes due to carry from LDAC 54 to MDAC 53 can be made to occur in the negative direction. Therefore, if the coupling capacitance C _c is set appropriately larger than the ideal value, that is, 2 ^l /2 ^l −1 × [unit capacitance C _p ], LDAC54
There is no jump in the positive direction at the joint between the output and the MDAC53. The nonlinear error of LDAC54 is
2 ^L resolution within 1/2LSB, MDAC53
If the value of capacitance C _c is set to cover the error of Namoto
By converting to the digital input of the DAC,
A DAC that satisfies linearity can be obtained.

FIG. 11 shows an example in which the DA converter is not configured in the form of upper and lower parts as shown in FIG. 10, but is configured with a series of capacitance strings.
Here, analog switches S _L0 , S _L1 , ...,
S _Ll-1 , S _M0 , S _M1 , . . . , S _Mn-1 are controlled in the same way as in the case of FIG. 10 to perform successive approximation. Capacity C ₀₀ ,
C _L1 ,..., C _Ll-1 ; C _M0 , C _M1 ,..., C _Mn-1 are 1.1C, 1.1C, 2.2C, ..., respectively, as shown in the figure.
(1.1×2 ^l ) C; 2 ^l C, 2 ^l+1 C, ..., 2 ^m+l-1 C. The lower digit part of the capacitance C ₀₀ to _{C Ll-1} corresponds to the lower DA converter, and its full scale is, for example, l=
3, it is (8.8C/128.8C) V _ref , and the upper
Capacitance of upper digit part corresponding to DA converter C _M0 ~
One step in C _Mn-1 , for example (8C/128.8C) when m=4, is set larger than V _ref . The DA converters of this example are MDAC53 and LDAC5 shown in Figure 9.
4 can be used in place of 4, thereby producing the same
A DA converter can be configured.

As described above, according to the present invention, the storage capacity of the storage circuit can be significantly reduced. In other words, the storage capacity of the storage circuit in the present invention is (number of bits of upper DAC) x (number of bits representing the shift amount), assuming that the original DAC has no nonlinear error and the addition rule is completely satisfied. . In contrast, the top
When storing all switching points and shift amounts according to the resolution of the DAC, the storage capacity of the memory circuit is (resolution of the upper DAC) x (number of bits representing the shift amount) + (resolution of the upper DAC). )×(number of bits representing the switching point), and it can be seen that the storage capacity is significantly reduced by the present invention. Also,
If the addition rule is not satisfied, (number of bits of upper DAC) × (number of bits representing the shift amount of each bit) + (resolution of upper DAC) × (number of bits representing the shift amount for nonlinear error) . Most of the shift amount of any code is due to "jump",
The amount due to nonlinear errors is very small. If one jump is 10LSB and the number of bits of the upper DAC is 8 bits, the maximum jump amount is 256 x 8LSB, or
11 bits, but the nonlinear error is 3 to 5 bits.
It can be suppressed to about a bit. Therefore, the degree of improvement is large in this case as well.

Regarding the conversion speed, in this invention, the upper DAC
It is only necessary to access the memory circuit a few times and perform processing such as addition to the readout output.
As in the case where all switching points and shift amounts are stored in accordance with the resolution of the DAC, a memory circuit that stores switching points is accessed as many times as the resolution of the upper DAC, and the readout output and input code are accessed. The conversion speed can be significantly reduced compared to when comparing .

[Brief explanation of drawings]

Fig. 1 is a characteristic diagram showing an example of the characteristics of a 3-bit upper DAC to explain the principle of code conversion according to the present invention, Fig. 2 is a partially enlarged view of Fig. 1, and Fig. 3 is a code diagram according to the present invention. Flowchart for explaining the conversion procedure; FIG. 4 is a block diagram showing an example of the code converter according to the present invention; FIG. 5 is an explanatory diagram of the operation sequencer of the code converter shown in FIG. 4; FIG. 7 is a circuit diagram showing a specific example of the two sequencers shown in FIG. 4, FIG. 8 is a timing chart for explaining the operation of the sequencers shown in FIGS. 6 and 7, and FIG. 9 is a diagram of the DA converter of the present invention. Block diagrams showing schematic configuration examples, FIGS. 10 and 11
The figure is a circuit diagram showing two examples of local DACs. 1...Digital input terminal, 2...Analog output terminal, 4...Digital adder, 5A, 5B...
...Memory circuit, 6A, 6B...Bus selector, 7
A, 7B...Sequencer, 8...Latch, 9A~
9G... Control signal line, 11-18... NAND gate, 19, 20... AND gate, 21... Inverter, 22... Binary/decimal converter, 23... Counter, 24... ROM drive signal terminal , 25...
Addition input terminal, 26A, 26B...Select signal output terminal, 27...Switching signal input terminal, 28...
Clock input terminal, 29...reset input terminal,
31, 32, 33...RS flip-flop, 3
4 to 41...D flip-flop with reset, 4
2...Inverter, 43...And gate, 51
... Digital input signal terminal, 52 ... Analog output signal terminal, 53 ... Upper DAC, 54 ... Lower DAC, 55 ... Analog adder, 56 ... Code converter, 61 ... Digital input signal terminal,
62...Analog output signal terminal, 63...Reference voltage terminal, S _L0 , S _L1 ,..., S _Ll-1 ; S _M0 , S _M1 ,...
…, S _Mn-1 …Analog switch, C ₀₀ , C _L0 ,
C _L1 , ..., C _Ll-1 ; C _M0 , C _M1 , ..., C _Mn-1 ...
Capacitance, C _c ...Coupling capacitance.

Claims (1)

[Scope of Claims] 1. A first digital-to-analog conversion means that generates an analog output corresponding to the upper digit input, and a full-scale output that is always larger than one step of the first digital-to-analog conversion means to the lower input digit. a second digital-to-analog conversion means for generating an analog output corresponding to the second digital-to-analog conversion means; and an addition means for adding the output of the first digital-to-analog conversion means and the output of the second digital-to-analog conversion means to obtain an analog output signal. The characteristics obtained by extending the input/output characteristics of the second digital/analog conversion means are set as ideal characteristics, and the same analog output is obtained based on the input/output characteristics of the first digital/analog conversion means and the ideal characteristics. In the digital-to-analog converter, the digital-to-analog converter corrects an analog output error occurring at a bit switching point of the first digital-to-analog conversion means by determining a digital code difference between the two as a correction value and adding the correction value to the input code. a first means for decomposing the correction value into correction amounts corresponding to each bit of the first digital-to-analog conversion means and reading out the correction amounts; a second means for adding to the input code; and when the addition result obtained from the second means is "1", the addition result is used as a new input code, and when the addition result is "0", the original A third means for outputting the input code as it is as an input code; and a fourth means for sequentially energizing the first to third means from the upper digit to the lower digit of the first digital-to-analog conversion means. , A digital-to-analog converter, characterized in that each correction amount of the first digital-to-analog conversion means is added to the input code.