JPH05327505A - Serial/parallel a/d converter - Google Patents

Abstract

PURPOSE:To obtain a high precise serial/parallel A/D converter in which a small area and a low power consumption can be realized by decreasing the number of elements. CONSTITUTION:In the first conversion step, a course comparator 5 compares an inputted voltage, and selects a resistance block 4. In the second conversion step, a fine comparator 6 finely compares the voltage by using a block in the selected resistance block 4, and generates an error correction signal for correcting the error of a digital output generated by the course comparator 5. A course encoder 7 with an error correction inputs an error correction signal E and the output signal of the course comparator 5, searches a logical product by an inside logical product circuit, searches the logical sum of the outputs of the logical product circuit by a logical sum circuit, corrects the error, encodes the output signal of the course comparator 5, and outputs it. Thus, the error correction can be operated by the encoder 7 without using full adders, so that the number of the elements can be decreased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of an A / D converter, and more particularly to a serial-parallel type structure having a series of error correction circuits capable of improving the accuracy of digital output. The present invention relates to an A / D converter.

[0002]

2. Description of the Related Art Generally, a serial / parallel A / D converter performs conversion in a plurality of steps. In the first step,
Determine the range of the analog signal input voltage by comparing with the rough reference voltage, determine the approximate value of the analog signal, and in the next step, compare the reference voltage that is divided into the range and the input voltage of the analog signal. Determine detailed values.

In FIG. 12, the upper m bits and the lower n bits are converted in two steps (m + n).
An example of a specific configuration of the bit serial parallel A / D converter will be shown. In FIG. 12, 1 is an analog signal input terminal, and 2 is a reference voltage input terminal. Reference numeral 3 is an output terminal for A / D converting an analog signal input from the input terminal 1 and then outputting it as a digital signal. Reference numeral 4 is a resistance block composed of ladder resistors connected in series. The resistor block 4 is composed of 2 ^m blocks having 2 ⁿ ladder resistors, and has a total of 2 ^{(m + n)} resistors. For example, in the case of an 8-bit serial-parallel type A / D converter of upper 4 bits and lower 4 bits, it consists of 16 blocks having 16 ladder resistors, and there are 256 resistors in total. Reference numeral 5 is a coarse (COARSE) comparator. The coarse comparator 5 compares the input voltage with the reference voltage across each of the 2 ^m blocks in the first conversion step, and determines which block the input voltage is in. Reference numeral 6 is a fine (fine) comparator. Fine comparator 6
In the second conversion step, the input voltage is compared with the reference voltage across the 2 ⁿ ladder resistors in the block selected by the resistance block selection signal S output from the coarse comparator 5. Determine which reference voltage is within. Reference numeral 7 is a course encoder. The coarse encoder 7 receives the output of the coarse comparator 5 and converts it into a high-order m-bit binary code. Reference numeral 8 is a fine encoder. The fine encoder 8 receives the output of the fine comparator 6 and converts it into a lower n-bit Binarina code. 81 is an error correction circuit. The error correction circuit 81 corrects the upper m-bit binary code output from the coarse encoder 7 by the error correction signal E output from the fine comparator 6. Reference numeral 9 is an output latch. The output latch 9 outputs the binary code output from the error correction circuit 81 and the fine encoder 8 as a digital signal. Although not shown, the above circuits operate in response to a plurality of clocks output from the clock generation circuit.

Next, the error correction of the conventional serial-parallel type A / D converter will be described. In the case of a serial / parallel A / D converter that performs conversion by dividing into two exchange steps, between a first conversion step for comparing the upper m bits and a second conversion step for comparing the lower n bits. There is a drawback that errors are likely to occur. That is, in the first conversion step, the coarse comparator 5 determines the upper limit voltage and the lower limit voltage to be input to the fine comparator 6, and in the next second step, the lower n bits are compared, and the fine comparator 6 determines the upper limit and the lower limit voltage. Determine the detailed value within the voltage range. If the fine comparator 6 has an input voltage of coarse course 7
If it is determined that the voltage is outside the upper limit voltage or the lower limit voltage determined by, the comparison of the upper m bits and the comparison of the lower n bits do not match, an error occurs, and the high order determined by the coarse comparator 5 is generated. There is an error in m bits. That is, although the resistance block should be one block above or below, the upper and lower voltage range limited by the coarse comparator 5 is shifted to the resistance block one block above or one block below. .. Therefore, by the error correction circuit, the upper side (high voltage side)
It is determined whether or not there is a shift to (1) or to the lower side (low voltage side), and 1 is added to or subtracted from the upper m-bit binary code according to the determination result, and the error is corrected.

FIG. 13 shows a circuit diagram of a fine comparator for explaining error correction in a serial / parallel A / D converter. In FIG. 13, reference numeral 20 is for converting the input voltage into the lower-order n-bit binary code D ^{n-1 to} D ⁰ in the voltage range (upper limit voltage V _UL to lower limit voltage V _LL ) limited by the coarse comparator 5. There are 2 ⁿ comparators. The coarse comparators 21 and 22 are comparators for error correction. The input voltage of the analog signal and the reference voltage generated by the ladder resistor 19 are input to each comparator from the input terminal 1, and the magnitudes of the voltages are compared. Reference numeral 23 is a determination circuit for determining the comparison result which is the output of the comparator. That is, the determination circuit 23 determines the comparator whose input voltage is smaller than the reference voltage. Reference numeral 24 is an error correction signal generation circuit for generating upper and lower error correction signals. When the determination circuit 23 determines that the input voltage is outside the upper limit voltage V _UL or the lower limit voltage V _LL of the comparator for n bits in the determination result of the comparator 20, that is, the determination result is for upper error correction. If it is a comparator, the signal E1 which is a +1 correction signal is set to 1 (High),
When the determination result is the lower error correction comparator, the signal E2, which is a -1 correction signal, is set to 1 (High). The correction signals E1 and E2 are output to the correction comparator 2
It can be easily generated by taking the logical sum of the judgment results of 1 and 22. Further, when it is determined that the voltage is inside the upper limit voltage V _UL or the lower limit voltage V _LL , that is, when both error correction signals are 0 (Low), no error has occurred, and thus it is a 0 correction signal. Signal E3
Is generated. This can be easily generated by taking the logical product of the judgment results of the error correction signals E1 and E2. In this conventional serial-parallel type A / D converter, only upper and lower 1-bit corrections of +1 correction and -1 correction are performed. However, regarding the expansion of the comparators 21 and 22 when performing multi-bit correction, an error occurs. Comparators 21 and 2 for correction
The larger the number of 2, the wider the range in which the error can be corrected.

These generated error correction signals E1 ...
E3 is directly input to the error correction circuit 81. When the correction signal E1 is 1, 1 is added to the upper m bits of the binary code. When the correction signal E2 is 1, 1 is subtracted from the binary code of the upper m bits (here, -1 is added). When the correction signal E3 is 1, both the correction signals E1 and E2 are 0, and it is determined that the input voltage is inside the upper limit voltage V _UL or the lower limit voltage V _LL , and the upper m-bit binary code Is output as is.

For example, when the upper 4 bits are judged by the coarse comparator 5, the upper 4 bits binary code (right LSB) output from the coarse encoder 7
Is '1011' (11), correction is performed as follows.

When the correction signal E1 = 1, 1 is added to the binary code output by the coarse encoder 7.

[0009]

[Equation 1]

As a result, the upper 4-bit binary code is set to '1100' (12).

When the correction signal E2 = 1, -1 is added to the binary code output by the coarse encoder 7.

[0012]

[Equation 2]

As a result, the upper 4-bit binary code is set to '1010' (10).

When the correction signal E3 = 1, 0 is added.

[0015]

[Equation 3]

As a result, the upper 4-bit binary code is set to '1011' (11).

[0017]

The serial-parallel type A / D converter having the conventional error correction circuit is configured as described above, and 1 is added to or subtracted from the upper m-bit binary code by error correction. Error correction circuit 81
Requires multiple full adders. 14 and 15 show an error correction circuit and a full adder used in the error correction circuit. FIG. 14 is a diagram showing the configuration of the error correction circuit. In FIG. 14, 82 is a full adder and 83 is an OR gate. The error correction circuit is a 4-bit circuit. The output signals C0 to C3 of the coarse encoder are input to the input terminal A of each full adder 82, the correction signal E2 or the logical sum of the correction signals E1 and E2 is input to each input terminal B, and the input terminal C is input. A carry signal CI is input to. FIG. 15 is a diagram showing an example of the full adder.
The full adder shown in FIG. 15 is a Neumann type full adder.
In FIG. 15, 82a and 82b are OR gates and 82c.
.About.82f are AND gates, 82g and 82h are NOR gates, and 82i and 82j are inverters. In other words, as in the above example, the binary code of the upper m bits is' 000.
Since m full adders are required to add the three types of signals of 1 ',' 1111 ', and' 0000 ', the number of elements increases as well as the number of elements increases. There is a problem that the circuit area of the D converter becomes large.

Such a problem becomes remarkable because the number of full adders increases as the number of bits increases in order to improve the accuracy of the serial-parallel A / D converter.

The present invention has been made in order to solve the above problems, and by performing error correction without using a full adder, the number of elements is small, the area is small, and the power consumption is high and the accuracy is high. A serial-parallel type A / D converter is provided.

[0020]

A serial / parallel A / D converter according to a first aspect of the present invention is a serial / parallel A / D converter for converting an analog signal into a digital signal in a plurality of conversion steps. Then, in the first conversion step, first comparing means for comparing the input analog signal with a reference voltage,
In a second step, determining second range comparing means for comparing the analog signal with a reference voltage in the range limited by the first comparing means, and the range limited by the first comparing means. The correction signal generating means for outputting the correction signal for detecting and correcting the error of the first comparing means, and the output signal of the first comparing means and the correction signal are inputted to the first An encoding circuit is provided which has a logical product circuit for taking the logical product of the output signal of the comparison means and the correction signal, and comprises an encoding means for encoding the output signal of the first comparison means, wherein the encoding means and the correction signal are provided. An error in the output of the first comparing means is corrected by the output signal of the first comparing means.

A serial-parallel type A / D converter according to a second aspect of the present invention is a serial-parallel type A / D converter for converting an analog signal into a digital signal in a plurality of conversion steps. A first comparing means for comparing the input analog signal with a reference voltage in the step, and a second comparing step for comparing the analog signal with the reference voltage in a range limited by the first comparing means in the second converting step. Two
And a correction signal generating means for outputting a correction signal for detecting and correcting an error of the first comparing means by determining the range limited by the first comparing means, Correction signal combination means connected to the correction signal generation means and combining the correction signals output from the correction signal generation means to create a new signal;
An AND circuit for taking the logical product of the output signal of the first comparator and the output signal outputted by the correction signal combination means, and an OR circuit for taking the logical sum of the output signals of the AND circuit, Encoding means for encoding the output signal of the first comparing means, wherein the encoding means uses the output signal of the correction signal combining means and the output signal of the first comparing means to output the first comparing means. It is characterized by correcting an output error.

A serial-parallel A / D converter according to a third aspect of the present invention is a serial-parallel A / D converter that converts an analog signal into a digital signal in a plurality of conversion steps. In the step, first comparing means for comparing the input analog signal with a reference voltage, and in the second step, a second comparing means for comparing the analog signal with the reference voltage in a range limited by the first comparing means. And a correction signal generating means for outputting a correction signal for detecting and correcting an error of the first comparing means by determining the range limited by the first comparing means, An output signal of the first comparator and the correction signal output by the correction signal generating means are input as address signals, and a memory is provided for outputting data corresponding to the address signals. And a encoding unit for encoding the output signal of the comparison means, said encoding means, and outputs a signal obtained by correcting the error of the output of said first comparing means by the output of the memory.

A serial-parallel A / D converter according to a fourth aspect of the present invention is a serial-parallel A / D converter that converts an analog signal into a digital signal in a plurality of conversion steps. In the step, first comparing means for comparing the input analog signal with a reference voltage, and in the second step, a second comparing means for comparing the analog signal with the reference voltage in a range limited by the first comparing means. And a correction signal generating means for outputting a correction signal for detecting and correcting an error of the first comparing means by determining the range limited by the first comparing means, The output signal of the first comparator is input, and the output signal of the first comparator is encoded based on the output signal of the first comparator without error correction processing and the encoded signal and the first signal. Ratio of And a logic circuit for generating an encoded signal by performing error correction processing on the output signal of the converter and encoding the encoded signal, and selectively outputting the encoded signal according to the correction signal. And an encoding means for encoding.

[0024]

The first comparing means in the first aspect of the invention compares the input analog signal with the reference voltage in the first converting step, and the analog comparing with the second comparing means in the second step. Limit the range of signals. Then, the correction signal generating means outputs a correction signal for detecting and correcting an error of the first comparing means by judging the range limited by the first comparing means. Next, by the logical product circuit of the encoding means,
The logical product of the output signal of the first comparator and the correction signal output from the correction signal generating means is taken, and for example, the output signal of the logical product circuit is encoded by the logical sum circuit to output the output signal of the first comparing means. It is possible to obtain a digital signal that has been corrected.

The first comparison means in the second invention compares the input analog signal with the reference voltage in the first conversion step, and the second comparison means in the second conversion step. Limit the range of analog signals. Then, the correction signal generating means determines the first range by determining the range limited by the first comparing means.
And outputs a correction signal for detecting and correcting an error in the comparing means of FIG. Next, in the correction signal combination means connected to the correction signal generation means, the correction signal output from the correction signal generation means is combined to create a new signal. The logical product circuit of the first encoding means corrects the error of the first comparing means by taking the logical product of the output signal of the first comparator and the output signal output by the correction signal combining means, and further, A digital signal corrected by obtaining the logical sum of the output signal of the logical product circuit and the output signal of the logical product circuit is obtained by the logical sum circuit of the encoder unit 1. By optimizing the configuration of the logic circuit as described above, it is possible to obtain a digital signal in which the number of elements is reduced and the output error of the first comparison means is corrected.

The first comparing means in the third aspect of the invention compares the input analog signal with the reference voltage in the first converting step, and the analog comparing with the second comparing means in the second step. Limit the range of signals. Then, the correction signal generating means outputs the correction signal for detecting and correcting the error of the first comparing means by judging the range limited by the first comparing means. Next, the memory included in the encoding means inputs the output signal of the first comparator and the correction signal output by the correction signal generating means as an address signal, and outputs data corresponding to the address signal. By storing in the memory all the data resulting from the combination of the output signal of the first comparator and the correction signal, the signal encoded by correcting the error of the output of the first comparing means is encoded by the encoding means. Can be output.

The first comparing means in the fourth aspect of the invention compares the input analog signal with the reference voltage in the first converting step, and in the second step, compares the analog signal with the second comparing means. Limit the range of signals. Then, the correction signal generating means outputs the correction signal for detecting and correcting the error of the first comparing means by judging the range limited by the first comparing means. In a logic circuit included in the encoding means, an encoded signal obtained by encoding the output signal of the first comparator without error correction processing by the input output signal of the first comparator and the output of the first comparator. An error correction process is performed on the signal to generate an encoded signal.
Further, by selectively outputting the encode signal by the correction signal input to the logic circuit, it is possible to output the signal in which the error of the output of the first comparing means is corrected from the encoding means.

[0028]

1 is a block diagram showing the configuration of a serial / parallel A / D converter according to a first embodiment of the present invention. The serial-parallel A / D converter according to the first embodiment uses an error-correcting encoder including a circuit for taking a logical product and a circuit for taking a logical sum of the outputs of the logical product circuits. , A serial-parallel type A / D converter capable of performing error correction without using a full adder.

Here, the conversion is divided into two steps as in the conventional case, and the upper m bits and the lower n bits of (m
+ N) An example of a serial / serial A / D converter is shown. In FIG. 1, 1 is an analog signal input terminal, and 2 is a reference voltage input terminal. Reference numeral 3 is an output terminal for A / D converting an analog signal input from the input terminal 1 and then outputting a digital signal. Reference numeral 4 is a resistance block composed of ladder resistors connected in series. Resistance block 4
Consists of 2 ^m blocks with 2 ⁿ ladder resistors, for a total of 2 ^{(m + n)} resistors. Reference numeral 5 is a course comparator. The coarse comparator 5 compares the input voltage with the reference voltage across each of the 2 ^m blocks in the first conversion step, and determines which block the input voltage is in. 6 is a fine comparator. In the second conversion step, the fine comparator 6 compares the reference voltage across the 2 ⁿ ladder resistors forming the block selected by the resistor block selection signal S output from the coarse comparator 5 with the input voltage. , Determine which reference voltage the input voltage is within. 7 is a course encoder with error correction. The coarse encoder with error correction 7 receives the output of the coarse comparator 5 and converts it into a high-order m-bit binary code, and corrects the high-order m-bit binary code by the error correction signal E output from the fine comparator 6. 8
Is a fine encoder. The fine encoder 8 receives the output of the fine comparator 6 and converts it into a binary code of lower n bits. Reference numeral 9 is an output latch. The output latch 9 outputs the binary code output from the error-correcting coarse encoder 7 and the fine encoder 8 as a digital signal. Although not shown, each of the above circuits operates in response to a plurality of clocks output from the clock generation circuit.

Next, a specific configuration of the encoder with error correction of the serial / parallel type A / D converter shown in FIG. 1 will be described with reference to FIG. Here, in order to simplify the explanation, the output of the coarse comparator 5 is a serial / parallel type A / A of the upper 2 bits.
An example of a D converter is shown. In FIG. 2, A3 to A0 are the determination results of the output of the course comparator 5, which are '000.
1 '(0),' 0010 '(1),' 0100 '
There are four possible ways (2) and '1000' (3).
The numbers in parentheses () indicate the upper 2 bits in decimal. C1,
C0 is an output signal of the course encoder 7. The output signals C1 and C0 are high-order 2-bit binary code (right side LSB) '0 corresponding to the output of the coarse comparator 5.
0 '(0),' 01 '(1),' 10 '(2),' 1
1 '(3) is represented. E1 is a +1 correction signal. When the correction signal E1 is 1 (High), 1 is added to the binary code of the upper 2 bits. E2 is a -1 correction signal.
When the correction signal E2 is 1, 1 is subtracted from the upper 2 bits of the binary code. E3 is a 0 correction signal. When the correction signal E3 is 1 (High), the binary code of the upper 2 bits is output from the coarse encoder 7 as it is. Further, in FIG. 2, 21 is a course comparator 5.
AND for the logical product of the output signal of
Circuit. The AND circuit 21 has a plurality of AND gates 21.
a to 21h. 22 is an OR circuit for taking the logical sum of the outputs of the AND circuit 21. OR circuit 2
2 is composed of transistors 22a to 22j.

Next, the operation of the course encoder with error correction 7 will be described. For example, the output signals A3 to A0 of the coarse comparator 5 are '0100' (2), and the correction signal E1
Is 1 (High), AND gate 21a in AND circuit 21 and OR circuit 22, transistor 22c,
The output of each 22g becomes 1 (High), and as a result, the upper 2 bits of the binary code C1 and C0 are "1".
1 '(3), and the output signals C1 and C0 are corrected by +1 and output from the coarse encoder 7.

Next, the output signal A3 of the coarse comparator 5
~ A0 is '0100' (2) and the correction signal E2 is 1
In the case of (High), the outputs of the AND gate 21e and the transistor 22h in the AND circuit 21 and the OR circuit 22 become 1 (High), and as a result, the binary code of the upper 2 bits becomes '01' (1), and the output Signal C
1 and C0 are corrected by -1 and output from the course encoder 7.

Further, the output signal A of the coarse comparator 5
When 3 to A0 are '0100' (2) and the correction signal E3 is 1 (High), the AND circuit 22 OR circuit 23
The outputs of the AND gate 21g and the transistor 22d in the inside become 1 (High), and as a result, the binary code of the upper 2 bits becomes "10" (2), and the output signals C1 and C
2 is output as it is.

Next, a serial / parallel type A / D converter according to a second embodiment of the present invention will be described with reference to FIG. The serial-parallel type A / D converter according to the second embodiment is provided with an error correction signal circuit to reduce the circuit for taking the logical product and the circuit for taking the logical sum of the outputs of the logical product circuit, As a result, the serial-parallel type A / D converter can perform error correction without using a full adder by using an encoder with error correction having a small area. In FIG. 3, 31
Is an error correction signal circuit that forms and outputs a new signal based on the error correction signal E, and 32 outputs a digital signal that is error-corrected by the output signal of the error correction signal circuit 31 and the output signal of the coarse comparator 5. This is a course encoder 32 with error correction. The other reference numerals that are the same as those in FIG. 1 indicate the same or corresponding portions as those in FIG. 1, and the other configurations are the same as those in FIG.

The error correction signal circuit 31 will be described with reference to Table 1 and FIG. Here, in order to simplify the explanation, the output of the coarse comparator 5 is a serial-parallel type A whose upper 2 bits are.
An example of a / D converter is shown.

[0036]

[Table 1]

In Table 1, A3 to A0 are the determination results of the output of the coarse comparator 5, which are '0001' according to the comparison result of the reference voltage and the input voltage of the analog signal.
(0), '0010' (1), '0100' (2),
There are four possibilities of '1000' (3). The numbers in parentheses () indicate the upper 2 bits in decimal. C1 and C0 are output signals of the coarse encoder 32. Output signals C1 and C
0 is a binary code (right side LSB) of upper 2 bits corresponding to the output of the coarse comparator 5, and is "00".
(0), '01' (1), '10' (2), '11'
It represents (3). E1, E2 and E3 are + 1,-
1,0 correction signal.

Table 1 focuses on the position of "1" (High) of each signal (a signal indicating the judgment result of the output of the comparator, an error correction signal, an output signal of the coarse encoder). For example, when the signal A1 indicating the determination result of the output of the comparator is “1” (High), the coarse encoder 3
For the output signals C1 and C0 of 2, the output signals of the coarse comparator 5 are respectively corrected by +1, -1, and 0, and then "10".
There are three possible ways: (2), '00' (0), and '01' (1). Therefore, both the signal A1 and the correction signal E1 are 1
At this time, focusing on the position where the output signal C1 is 1, that is, "1" (High), the intersection of the output signal C1 and the signal A1 in Table 1 becomes the correction signal E1. Further, the intersection of the signal A1 and the output signal C0 in Table 1 becomes the correction signal E3. The same applies to other cases.

The logical operation of the error correction signal circuit can be obtained from Table 1. That is, the output signal C1 is set to "1" (High
The logical expression for h) is expressed as follows.

[0040]

[Equation 4]

Similarly, the output signal C1 is set to "1" (High).
The logical expression for h) is expressed as follows.

[0042]

[Equation 5]

From these logical expressions, (E1 + E3), (E
The signals given by (2 + E3) and (E1 + E2) are S1, S2, and S3, respectively. By generating these signals S1 to S3 by the error correction signal circuit 31, the logical expressions shown in Formula 4 and Formula 5 can be rewritten as follows.

[0044]

[Equation 6]

[0045]

[Equation 7]

Next, a circuit diagram of the error correction signal circuit 31 is shown in FIG. In FIG. 4, 31a to 31c are OR gates. Correction signal E1 input to the error correction circuit 31
Among E3 to E3, the correction signals E1 and E3 are output as they are. At the same time, in the OR gates 31a to 31c,
The signals S1 to S3 are newly generated using the correction signals E1 to E3.

Then, the correction signals E1 and E3 and the signal S1
The logical expressions of Expressions 6 and 7 are realized by the encoder 32 with error correction by using S3. The configuration of the encoder 32 with error correction is shown in FIG. The error correction encoder 32 includes an AND circuit 32 for logical product of the output signal of the comparator 5 and the output signal of the error correction signal circuit 31,
OR circuit 3 for taking the logical sum of the outputs of the AND circuits 32
It consists of three. The AND circuit 32 inputs the output signals A3 to A0 of the comparator 5 to one input terminal and outputs the output signals E1 and E of the error correction signal circuit 31 to the other input terminal.
AND gates 32a to 32g for inputting S3 and S1 to S3
It is composed of. The OR circuit 22 is a transistor 33a
It is composed of ~ 33g.

Next, referring to FIG. 6, the error correction signal circuit 31
Shows the effect of. In FIG. 6, each input signal is shown in FIG.
Is the same as. FIG. 6A shows a schematic diagram of the encoder with error correction of FIG. Here, ● is an AND gate for the logical product of the comparator output and the error correction signal,
◯ is the input terminal of the OR gate for taking the logical sum of the outputs of the AND gates. The OR gates forming the OR circuit 22 are two, that is, a 5-input OR gate that outputs the output signal C1 and a 5-input OR gate that outputs the output signal C0.
From this, there are 8 AND gates and 1 transistor.
It turns out that 0 pieces are required.

FIG. 6B shows a schematic diagram of an encoder with error correction when an error correction signal circuit is provided. Here, ● is an AND gate for the logical product of the comparator output and the error correction signal, and ◯ is an input terminal of the OR gate for taking the logical sum of the outputs of the AND gates. The OR gate of the OR circuit 33 is a 3-input OR gate that outputs the output signal C1 and a 3-input OR gate that outputs the output signal C0.
It consists of a gate. From this, the AND gate is 7
It turns out that seven transistors are required.

The effect of reducing the number of gates of the error correction signal circuit 31 is small when the number of gates of the error correction signal circuit 31 is included in the case of 2 bits as in the example of FIG. 6, but the serial / parallel type A / D conversion is performed. The effect is greater as the number of bits increases to improve the accuracy of the device, and the number of times of driving at the output terminal of the comparator decreases, so that the speed of the AND circuit and the OR circuit can be increased with the same drive capacity. ..

Next, a serial / parallel type A / D converter according to a third embodiment of the present invention will be described with reference to FIG. FIG. 7 is a block diagram showing the configuration of a serial / parallel A / D converter according to the third embodiment of the present invention. In FIG. 7, reference numeral 51 is an error correction memory for inputting the output signal of the coarse comparator 5 and the correction signal E and outputting a corrected digital signal,
Other reference numerals that are the same as those in FIG. 1 indicate the same or corresponding portions as in FIG. 1, and the configuration other than the error correction memory 51 is the same as in FIG. Series-parallel A / D according to the third embodiment
The converter stores a fine comparator 6 having means for generating an error correction signal in the next conversion step in order to correct the error of the digital output generated in the first conversion step, and the error-corrected signal. An error correction memory 51 is provided, and the error correction memory 51 is controlled by the output of the coarse comparator 5 and the error correction signal E, which is a serial-parallel A / D converter.

Next, the error correction memory 51 will be described with reference to FIG. Here, in order to simplify the explanation, the output of the coarse comparator 5 is a serial / parallel type A / A of the upper 2 bits.
An example of a D converter is shown. In FIG. 8, A3 to A0 are output signals indicating the determination result of the output of the coarse comparator 5, and according to the comparison result of the reference voltage and the input voltage of the analog signal, "0001" (0), "0010" (1), '0
Four types of 100 '(2) and' 1000 '(3) can be considered. The numbers in parentheses () indicate the upper 2 bits in decimal.
C1 and C0 are output signals of the coarse encoder, and output signals C1 and C0 are high-order 2-bit binary codes (right side LSB) of "00" (0) and "01" (corresponding to the output signals of the coarse comparator. 1), '10' (2),
Indicates '11' (3). E1, E2 and E3 are +
1, -1,0 correction signal. Further, 52 is a correction signal E
1 to E3 and output signals A3 to A of the coarse comparator 5
An address decoder which inputs 0 as one address signal and decodes this address signal, and 53 is a memory cell array which outputs data selected by the output signal of the address decoder 52. The memory cell array 53 has +1, -1, 0 corresponding to the output signals A3 to A0, respectively.
All data corresponding to the correction is stored.

Next, the operation of the correction memory 51 will be described.
In the correction memory 51, since the determination results A3 to A0 of the coarse comparator output and the correction signals E1 to E3 as described above are used for the address signal, twelve word lines a1 to a12 are connected to the address decoder 52. You will need it.

Here, for example, the outputs A3 to A0 of the course comparator are "0100" (2), and the correction signal E1
Is 1 (High), the word line a7 is "1" (H
output) and outputs C1 and C of the memory cell array 53
0 becomes '11'. Similarly, the outputs A3 to A0 of the coarse comparator are '0100' (2), and the correction signal E2
Is 1 (High), the word line a8 is "1" (H
output) and outputs C1 and C of the memory cell array 53
0 becomes '01'. Similarly, the outputs A3 to A0 of the course comparator are '0100' (2), and the correction signal E3
Is 1 (High), the word line a9 is "1" (H
output) and outputs C1 and C of the memory cell array 53
0 becomes '10'.

Next, a serial / parallel A / D converter according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 9 is a block diagram showing the configuration of the serial / parallel A / D converter according to the fourth embodiment. In FIG. 9, reference numeral 71 is an input of the output signal of the coarse comparator 5 and a signal corresponding to the output signal +
A comparator output circuit for outputting a signal corrected by 1, -1, 0, 72 receives an output signal of the comparator output circuit 71, and selectively outputs the corrected output signal according to the correction signal E. The same reference numerals as those in FIG. 1 denote the same or corresponding portions as those in FIG.

The serial-parallel type A / D converter according to the fourth embodiment is provided with a comparator output circuit 71 and an output control circuit 72, and the comparator output circuit 71 produces a combination of +1, -1, 0 correction of the comparator output. , Error correction signal E
Based on the above, the serial / parallel A / D converter can perform error correction without using the full adder by controlling the combination result by the control circuit 72. Other configurations are the same as those in FIG.

The comparator output circuit 71 will be described with reference to Table 2. Here, for simplification of description, an example of a serial-parallel type A / D converter in which the output of the coarse comparator 5 is the upper 2 bits is shown.

[0058]

[Table 2]

In Table 2, A3 to A0 are output signals indicating the determination result of the output of the coarse comparator, and are "0" according to the comparison result of the reference voltage and the input voltage of the analog signal.
001 '(0),' 0010 '(1),' 0100 '
There are four possible ways (2) and '1000' (3).
The numbers in parentheses () indicate the upper 2 bits in decimal. C1,
C0 is an output signal of the coarse encoder. Output signal C
1 and C0 are high-order 2-bit binary code (right side LSB) '0 corresponding to the output signal of the coarse comparator.
0 '(0),' 01 '(1),' 10 '(2),' 1
1 '(3) is represented. E1, E2 and E3 are +1, respectively
-1,0 correction signal.

Table 2 focuses on the position of "1" (High) of each signal (a signal indicating the judgment result of the output of the comparator, an error correction signal, an output signal of the coarse encoder). For example, when the correction signal E1 is "1" (High), the correction signal E1 is +1 correction, and the output signals C1 and C0 of the coarse encoder are "01" according to the signals A0, A1 and A2 indicating the determination result of the output of the comparator. (1), '10'
There are three possible ways (2) and '11' (3). Therefore, if the output signal C0 is 1, that is, the position of "1" (High) when the signal A1 or A2 and the correction signal E1 are both 1, the intersection of the output signal C1 and the correction signal E1 in Table 2 is the signal. A1 and A2. In addition, the correction signal E1 in Table 2
And the output signal C0 intersect at points A0 and A2. The same applies to other cases.

The logical operation of the comparator output circuit can be obtained from Table 2. That is, the correction signal E1 is "1" (Hi
gh), the results of A1 + A2 and A0 + A2 are output as output signals C1 and C0. Similarly, when the correction signal E2 is “1” (High), the results of signals A3 and A2 are output signals C1 and C0. Is output.

Next, the comparator output circuit 71 shown in FIG.
The operation of the output control circuit 72 will be described with reference to FIG. In FIG. 10, 71 is a coarse comparator output circuit, and 71a to 71d are OR gates. Reference numeral 72 is an output control circuit, and 72a to 72c are switch circuits to which an error correction signal is input.

Here, for example, when the output signals A3 to A0 of the coarse comparator 5 are '0100' (2) and the correction signal E1 is 1 (High), the OR gates 71a and 71b of the comparator output circuit 71 are used. , 71c become “1” (High), and only the switch circuit 72a of the output control circuit 72 is turned on. As a result, the upper 2-bit binary codes C1 and C0 become “11” (3), and the output control circuit 7 is corrected by +1.
It is output from 2.

Next, when the correction signal E2 is 1 (High), only the switch circuit 72b of the output control circuit 72 is turned on, and as a result, the upper 2 bits of the binary code C1, C0 are "01" (1 ), And is corrected by -1 and output from the output control circuit 72.

Further, when the correction signal E3 is 1 (High), only the switch circuit 72c of the output control circuit 72 is turned on, and as a result, the binary codes C1 and C0 of the upper 2 bits are '10' (2). And is corrected to 0 and output from the output correction circuit.

In this example, overflow and underflow are not taken into consideration. For example, the coarse comparator 5
When the output signals A3 to A0 of "0100" (3) and the correction signal E1 is 1 (High), the line transmitting the output signal A3 becomes "1" (High), and as a result, the upper 2 bits Binary codes C1 and C0 are '00'
(0). The same applies to the case of underflow. However, for example, a detection circuit for detecting and determining the output of the coarse comparator 5 is provided, and a new output pin is further provided so that the coarse comparator outputs A3 to A0 are '100.
If the correction signal E1 is 0 (3) and the correction signal E1 is 1 (High), the binary codes C1 and C0 of the upper 2 bits are "0".
At the same time as 0 '(0), the overflow information is output from the detection circuit to the newly provided output pin, so that the overflow can be easily dealt with when necessary. The same applies to the case of underflow.

Next, a serial / parallel A / D converter according to the fifth embodiment will be described with reference to FIG. The serial / parallel A / D converter of the fifth embodiment has the same configuration as that shown in FIG. Fifth
The serial / parallel A / D converter of the embodiment is different from that of the fourth embodiment in that the configuration of the comparator output circuit and the configuration of the output control circuit are different. FIG. 11 is a circuit diagram showing the configurations of the comparator output circuit and the output control circuit. Here, for simplification of description, an example of a serial-parallel type A / D converter in which the output of the coarse comparator 5 is the upper 2 bits is shown. In FIG. 11, output signals A3 to A0 indicating the determination result of the output of the coarse comparator, output signal C1 of the coarse encoder,
The C0 and + 1, -1,0 correction signals E1, E2, E3 are the same as in the fourth embodiment. Further, 73, 74, and 75 are logic circuits for generating signals according to +1, -1, and 0 corrections, respectively. An output control circuit 76 selectively outputs the signals input from the logic circuits 73, 74 and 75 in response to the error correction signal E. Logic circuits 73, 74, 7
5 are transistors 73a to 73d and 74a to 7 respectively.
4b and 75a to 75d. The output control circuit 76 is composed of switch circuits 76a to 76f and an inverter 77.

Here, for example, when the output signals A3 to A0 of the coarse comparator 5 are "0100" (2) and the correction signal E1 is 1 (High), the transistors 73a, 73b, to which the output signal A2 is input, 74b and 75c are turned on, 1 is output to the line connecting each transistor, and the output of the logic circuit 73 to which +1 correction is applied is “0”.
The output of the logic circuit 74 to which 0 ', -1 correction is applied is' 1.
The output of the logic circuit 75 to which 0 ', 0 correction is applied is'01'.
Becomes The switch circuit 7 of the output control circuit 76
6a and 76b are turned on, and only the output of the logic circuit 73 for +1 correction is input to the inverter circuit 77. As a result, the upper 2 bits of binary code C1, C0
Becomes '11' (3), and the binary code C1, C obtained by encoding the output signal of the coarse comparator 5 by -1 correction
0 is output.

Next, the output signal A3 of the course comparator 5
~ A0 is '0100' (2) and the correction signal E2 is 1 (H
In the case of (high), the switch circuits 76c and 76d of the output control circuit 76 are turned on, and only the output of the -1 correction logic circuit 74 is input to the inverter circuit 77. As a result, the upper 2 bits of the binary code C
1, C0 becomes '01' (1), and binary codes C1, C0 obtained by -1 correcting and encoding the output signal of the coarse comparator 5 are output.

Further, the output signal A of the course comparator 5
3 to A0 is '0100' (2) and the correction signal E3 is 1
In the case of (High), the switch circuits 76e and 76f of the output control circuit 76 are turned on, and only the output of the 0 correction logic circuit 75 is input to the inverter circuit 77. As a result, the upper 2 bits of the binary code C
1, C0 becomes '10' (2), and the binary code C obtained by correcting the output signal of the coarse comparator 5 by 0 and encoding
1, C0 is output.

In this example, overflow and underflow are not taken into consideration, but by providing an output pin and a detection circuit as in the fifth embodiment, it is possible to deal with overflow and underflow in a serial-parallel type. It can be an A / D converter.

In each of the above embodiments, the serial / parallel type A / D converter for performing conversion in two steps has been described, but the serial / parallel type A / D for performing conversion in more steps is described. It may be applied to a converter and has the same effect as that of each of the above-described embodiments.

Further, in each of the above-mentioned embodiments, the serial / parallel type A / D converter for performing the correction of the upper and lower 1 bits is explained, but it can be applied to the case of the correction of the multi-bit, and in that case as well. The same effect as that of each of the above-described embodiments is obtained.

[0074]

As described above, according to the serial-parallel type A / D converter of the invention described in claim 1, the range of the first comparing means is judged by judging the range limited by the first comparing means. A correction signal generating means for outputting a correction signal for detecting and correcting an error and a logical product circuit for taking a logical product by inputting the output signal of the first comparing means and the correction signal are provided. An encoding means for encoding the output signal of the comparing means,
The encoding means is configured to correct the error in the output of the first comparing means by the correction signal and the output signal of the first comparing means, and the logical product circuit of the encoding means causes the encoding means of the first comparator to operate. Since the digital signal obtained by correcting the output signal of the first comparison means is obtained by encoding the output signal, the conventional serial-parallel type A using the full adder is obtained.
Compared with the / D converter, the number of elements can be reduced, and there is an effect that high accuracy can be achieved with a small occupied area and low power consumption.

According to the serial-parallel A / D converter of the invention described in claim 2, the correction is connected to the correction signal generating means, and the correction signals outputted from the correction signal generating means are combined to create a new signal. A signal combination means, a logical product circuit for taking a logical product of the output signal of the first comparator and the output signal outputted by the correction signal combination means, and a logical sum circuit for taking a logical sum of the output signals of the logical product circuits. And encoding means for encoding the output signal of the first comparing means, wherein the encoding means outputs the output of the first comparing means by the output signal of the correction signal combining means and the output signal of the first comparing means. It is configured to correct an error, and the error of the first comparison means is corrected by taking the logical product of the output signal of the first comparator and the output signal output by the correction signal combination means, and further the logic product By taking the logical sum of the output signal of the path and the output signal of the AND circuit, a digital signal in which the error of the output of the first comparison means is corrected can be obtained, and the conventional serial-parallel using the full adder is obtained. The number of elements can be reduced as compared with the type A / D converter, and further, by optimizing the configuration of the logic circuit, the number of elements can be reduced, and high precision can be achieved with a small occupied area and low power consumption. There is.

According to the serial-parallel type A / D converter of the invention described in claim 3, the error of the first comparing means is detected and corrected by judging the range limited by the first comparing means. A correction signal generating means for outputting a correction signal for inputting the signal, and a memory for inputting the output signal of the first comparator and the correction signal output by the correction signal generating means as an address signal and outputting the data corresponding to the address signal. And encoding means for encoding the output signal of the first comparing means, wherein the encoding means is configured to output a signal in which an error in the output of the first comparing means is corrected by the output of the memory. Therefore, by storing all the data obtained by combining the output signal of the first comparator and the correction signal in the memory, the encoded signal is corrected by correcting the error in the output of the first comparing means. The number of elements can be reduced as compared with the conventional serial-parallel type A / D converter that uses a full adder, and high precision can be achieved with a small occupied area and low power consumption. There is an effect that can be.

According to the serial-parallel A / D converter of the invention described in claim 4, the error of the first comparing means is detected and corrected by judging the range limited by the first comparing means. A correction signal generating means for outputting a correction signal for inputting the signal and an output signal of the first comparator are input, and the output signal of the first comparator is directly encoded based on the output signal of the first comparator. When a signal and the output signal of the first comparator are assumed to be erroneous, the error is corrected to generate an encoded encoded signal, and a logic circuit for selectively outputting the encoded signal by the correction signal is provided. And an encoding means for encoding the output signal of the first comparison means, and in the logic circuit, the output signal of the first comparator is changed by the input output signal of the first comparator. Enco coded as is When the input signal and the output signal of the first comparator are assumed to be erroneous, the erroneous error is corrected and the encoded signal is generated, so that the conventional serial-parallel A / D converter is used. Without using a full adder for
A signal in which an error in the output of the first comparison unit is corrected can be output from the encoding unit, and the number of elements can be reduced as compared with the conventional serial-parallel A / D converter that uses a full adder. There is an effect that high accuracy can be achieved with a small occupied area and low power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a serial / parallel A / D converter according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an encoder with error correction which constitutes a serial / parallel A / D converter according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a serial / parallel A / D converter according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram of an error correction signal circuit which constitutes a serial / parallel A / D converter according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of an encoder with error correction which constitutes a serial / parallel A / D converter according to a second embodiment of the present invention.

FIG. 6 is a diagram for explaining the effect of the error correction signal circuit of the serial / parallel A / D converter according to the second embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a serial / parallel A / D converter according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of an error correction memory of a serial / parallel A / D converter according to a third embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a serial / parallel A / D converter according to a fourth embodiment of the present invention.

FIG. 10 is a serial / parallel A / D according to a fourth embodiment of the present invention.
FIG. 3 is a circuit diagram of a comparator output circuit and an output control circuit that form a converter.

FIG. 11 is a serial / parallel A / D according to a fifth embodiment of the present invention.
FIG. 3 is a circuit diagram of a comparator output circuit and an output control circuit that form a converter.

FIG. 12 is a block diagram showing a configuration of a conventional serial-parallel type A / D converter.

FIG. 13 is a diagram schematically showing a fine comparator that constitutes a conventional serial-parallel A / D converter.

FIG. 14 is a diagram for explaining an error correction circuit that constitutes a conventional serial-parallel A / D converter.

15 is a circuit diagram showing an example of a full adder used in the error correction circuit shown in FIG.

[Explanation of symbols]

 1 analog signal input terminal 2 reference voltage input terminal 3 digital signal output terminal 4 resistance block 5 coarse comparator 6 fine comparator 7 coarse encoder with error correction 8 fine encoder 9 output latch 31 error correction signal circuit 32 coarse encoder with error correction 51 error correction memory 71 comparator output circuit 72 output control circuit

Claims (4)

[Claims] 1. A serial-parallel A / D converter for converting an analog signal into a digital signal in a plurality of conversion steps, wherein the input analog signal is compared with a reference voltage in a first conversion step. Limited by the first comparing means, second comparing means for comparing the analog signal with a reference voltage in the range limited by the first comparing means in the second step, and the first comparing means And a correction signal generating means for outputting a correction signal for detecting and correcting an error of the first comparing means by determining the range, and an output signal of the first comparing means and the correction signal. An AND circuit for inputting the logical product of the output signal of the first comparing means and the correction signal, and an encoding means for encoding the output signal of the first comparing means, Encoding means, said correction signal and serial-parallel type A / D converter and correcting an error in the output of said first comparing means by an output signal of said first comparing means. 2. A serial-parallel type A / D converter for converting an analog signal into a digital signal in a plurality of conversion steps, wherein the input analog signal is compared with a reference voltage in the first conversion step. Limited by the first comparison means, second comparison means for comparing the analog signal with a reference voltage in the range limited by the first comparison means in the second conversion step, and the first comparison means Correction signal generating means for outputting a correction signal for detecting and correcting an error of the first comparing means by determining the corrected range, and the correction signal generating means connected to the correction signal generating means. Correction signal combining means for combining the correction signals output from the first comparator to create a new signal, and an output signal of the first comparator and the correction signal combining means. Encoding means for encoding the output signal of the first comparing means, which has a logical product circuit for taking a logical product with the output output signal and a logical sum circuit for taking a logical sum of the output signals of the logical product circuit. The encoding means includes a first output signal of the correction signal combination means and an output signal of the first comparison means.
A serial-parallel type A / D converter which corrects an error in the output of the comparing means. 3. A serial-parallel type A / D converter for converting an analog signal into a digital signal in a plurality of conversion steps, wherein the input analog signal is compared with a reference voltage in a first conversion step. Limited by the first comparing means, second comparing means for comparing the analog signal with a reference voltage in the range limited by the first comparing means in the second step, and by the first comparing means. And a correction signal generating means for outputting a correction signal for detecting and correcting an error of the first comparing means by determining the range, and an output signal of the first comparator and the correction signal generating means. Input the correction signal output by the as an address signal,
An encoding unit that has a memory for outputting data corresponding to the address signal, and that encodes an output signal of the first comparing unit, wherein the encoding unit outputs the memory to output the first comparing unit. A serial-parallel type A / D converter which outputs a signal in which an error in the output of the above is corrected. 4. A serial-parallel A / D converter for converting an analog signal into a digital signal in a plurality of conversion steps, wherein the input analog signal is compared with a reference voltage in a first conversion step. Limited by the first comparing means, second comparing means for comparing the analog signal with a reference voltage in the range limited by the first comparing means in the second step, and by the first comparing means. Correction signal generating means for outputting a correction signal for detecting and correcting an error of the first comparing means by determining the range, and inputting an output signal of the first comparator, Error correction processing is performed on the encoded signal obtained by encoding the output signal of the first comparator without performing error correction processing on the basis of the output signal of the first comparator and the output signal of the first comparator. A serial parallel circuit having a logic circuit for generating an encoded encoded signal and selectively outputting the encoded signal according to the correction signal, and an encoding unit for encoding the output signal of the first comparing unit. Type A / D converter.