JPS622490B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a digital-to-analog converter that has high resolution but does not satisfy accuracy, that is, does not satisfy linearity.
Regarding digital-to-analog converters (hereinafter abbreviated as DAC), which perform so-called digital trimming to correct linearity and improve accuracy, we have particularly improved the input code converter. The present invention relates to a digital-to-analog converter that increases the conversion speed.

The present inventors applied digital trimming to
As a PAC, in Japanese Patent Application No. 127239/1984, a first digital-analog converter (abbreviated as upper DAC) generates the output of the upper digit, and a first digital-analog converter (abbreviated as upper DAC) generates the output of the lower digit.
1 of the least significant digit digital input of the DAC (abbreviated as DAC)
A second digital signal that generates a full-scale output that is always larger than the bit-wise output value (1LSB value).
an analog converter; summing means for adding the output of the first digital-to-analog converter and the output of the second digital-to-analog converter to obtain an analog output signal;
An input code obtained by shifting the digital input signal by a predetermined value is input to the first and second digital-to-analog converters so that the relationship between the digital input signal and the analog output signal to the analog converter is approximately linear. We proposed a digital-to-analog converter equipped with a code converter.

Here, the upper DAC and lower DAC can be composed of the original DAC, and an example of the 3-bit characteristics of the upper DAC is shown in Figure 1.
The output change at the carry point of the input to the DAC is always reduced. In order to correct this characteristic to the ideal characteristic shown in FIG. 1, it is necessary to perform the following code conversion. That is, when the input codes at the positions where the correction amount switches are J ₀ , J ₁ , J ₂ , ..., respectively, and the input code is 0 to J ₀ , the shift amount C ₀ (=0), When J ₀ to _{J 1} , it is necessary to determine the shift amount from the input code as C ₁ , . . . and add the correction amount corresponding to the shift amount to the input code.

In that case, input codes J ₀ ~ J ₁ , J ₁ ~ _{J 2} , ...
The problem is to identify in which region it is located. In principle, the input code is successively compared with the switching point codes J ₀ , J ₁ , J _{2 ,} . It can be identified that it is between _q-1 and _Jq . However, in the worst case, the number of comparison operations will be equal to the number of switching points _Jq , that is, the number of times corresponding to the resolution of the upper DAC, and the above-mentioned DAC has the disadvantage of requiring a long processing time. be. Furthermore, the basic comparison operation can be realized by reading data indicating the switching point from the memory circuit, taking the one's complement of that data, and adding it to the input code; however, access to the memory circuit, Inversion of the read data and addition processing twice are required, which further increases the processing time. The above is a major hindrance to shortening the DA conversion time of the DAC proposed above. In addition, the configuration of the logic circuit for performing such processing becomes complicated, and there is a problem in that the storage capacity of the storage circuit becomes particularly large.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned problems and to provide a digital/analog converter capable of speeding up the DA conversion speed by making it possible to immediately determine the switching point from the digital signal of a part of the input code. The purpose is to provide a converter.

To achieve such an object, the present invention provides a first digital-to-analog converter that generates an output of the most significant digit, and a digital input of the least significant digit of the first digital-to-analog converter as an output of the least significant digit. a second digital-to-analog converter that generates a full-scale output that is always larger than the output value of 1 bit (1LSB value); an original digital-to-analog converter having an addition means for adding the outputs of the converter to obtain an analog output signal;
An input code obtained by shifting the digital input signal by a predetermined value is applied to the first and second digital-to-analog converters so that the relationship between the digital input signal to the digital-to-analog converter and the analog output signal is approximately linear. In a digital-to-analog converter having a code converter input to the digital-to-analog converter, the code converter converts the digital-to-analog conversion characteristics of the original digital-to-analog converter into the first digital-to-analog converter.
Corresponding to each region of each digital quantity equally divided with twice the resolution of the analog converter, the point at which the shift amount in that region switches in the characteristic corrected by the code shift in the code converter is stored in advance. , a switching point generation circuit for extracting switching point data in response to a portion of the digital input signal; and digitally comparing the portion of the digital input signal and the switching point data from the switching point generation circuit. , the amount of shift within the area is 2
A comparison circuit that specifies which one to select when there are different types, and a comparison circuit that stores the shift amount if there is one type of shift within the area corresponding to the area, and stores the shift amount if there are two types. a code shift amount generation circuit that stores in advance the shift amount specified by the comparison circuit and extracts a predetermined code shift amount in response to the digital input signal; the code shift amount generation circuit and the digital input signal; and an adder that performs digital addition of and supplies the addition result to the first and second digital-to-analog converters.

The present invention also provides an output value (1 LSB) of the digital input of the least significant digit in the upper digit part
(value of , and a code converter that inputs an input code obtained by shifting the digital input signal by a predetermined value to the original digital-to-analog converter, the code converter comprising: Corresponding to each region of each digital amount obtained by equally dividing the digital-to-analog conversion characteristics of the analog converter with twice the resolution of the original digital-to-analog converter, the characteristics corrected by the code shift in the code converter are a switching point generation circuit that stores in advance a point at which the shift amount changes within the area and extracts data at the switching point in response to a portion of the digital input signal; a portion of the digital input signal; The data at the switching point from the generation circuit is compared digitally, and the amount of shift within the area is 2.
A comparison circuit that specifies which one to select when there are different types, and a comparison circuit that stores the shift amount if there is one type of shift within the area corresponding to the area, and stores the shift amount if there are two types. a code shift amount generation circuit that stores in advance the shift amount specified by the comparison circuit and extracts a predetermined code shift amount in response to the digital input signal; the code shift amount generation circuit and the digital input signal; and an adder that performs digital addition of and supplies the addition result to the original digital-to-analog converter.

The present invention will be described in detail below with reference to the drawings.

FIG. 2 shows an embodiment of the basic configuration of the code converter in the digital-to-analog converter of the present invention, where 1 is the digital input signal terminal, and 2 is the original signal terminal.
A code conversion output signal terminal to the DAC, 3 a digital comparator, 4 a switching point generation circuit, 5 a code shift amount generation circuit, and 6 a digital adder. To explain the circuit operation, it is assumed that the number of bits of the original DAC is n bits, the number of bits of the upper DAC is m bits, and the number of bits of the lower DAC is l=n-m bits. Also, if the number of bits after correction is k, then
It is clear that the number of bits after correction is smaller than before correction, and k<n. Each area shown in Figure 1 corresponds to the resolution of the upper DAC in the original DAC, which is 2 ^m
Since this corresponds to twice the resolution, that is, 2 ^(m+1) , it is possible to identify the signal using the upper (m+1) bits of the input code. Therefore, as shown in Figure 1,
In response to the signal of the upper (m+1) bits of the input code, the switching point generation circuit 4, e.g.
The lower [n-(m+1)] bit signals of the switching point codes J ₀ , J ₁ , J ₂ , . . . are stored in the ROM. If there is no switching point in that area, 0 is stored. Similarly, the upper input code (m
+1) Corresponding to the bit signal, the code shift amount generation circuit 5 instructs the code shift amount generating circuit 5 to set the shift amount C ₀ =0, C ₁ ,
C ₂ , ... are memorized in advance.

When a digital input code is applied to terminal 1, the signal of its upper (m+1) bits is supplied to the switching point generation circuit 4, thereby specifying an area, and the switching point generation circuit 4 instructs a switching point in that area. In some cases, the lower order (n-m-
1) Outputs a bit signal, and outputs 0 if there is no switching point in that area. The digital comparator 3 converts the lower order (nm-
1) Compare the bit code data and the output from the switching point generation circuit 4, and if the input code data is larger, output a carry signal. That is,
If a switching point exists within that region, since there are two types of shift amounts within that region, it is possible to determine which of the two shift amounts to use by this comparison operation. Assuming that the smaller of the two shift amounts is stored in the code shift amount generating circuit 5 in correspondence with that area, when the input code is small, the shift amount is stored in the next area, and when the input code is large, the shift amount is stored in the next area. The code shift amount generation circuit is driven to output the corresponding shift amount. On the contrary, 2
Assuming that the larger of the two shift amounts is stored in the code shift amount generation circuit 5 corresponding to that area, when the input code is large, the shift amount corresponding to that area is stored, and when it is small, the shift amount corresponding to the previous area is stored. The code shift amount generation circuit 5 may be driven to generate the shift amount. Through the above operations, the shift amount to be corrected corresponding to each input code can be obtained from the code shift amount generation circuit 5. lastly,
The digital adder 6 adds the shift amount and the input code, and supplies the added output as an input code corrected according to the input code to a source DAC (not shown), which outputs the input code from the source DAC. To obtain analog output that correctly corresponds to the code. Note that the number of bits of the input code is the same as the original DAC.
Since the shift amount is set by the resolution of the original DAC, the adder 6 performs addition so that the most significant digits match.

FIG. 3 shows a specific circuit example of the digital comparator 3, where 11 is a carry adder from which only a carry signal is output. The switching point generating circuit 4 of this example is composed of a memory circuit that stores one's complement, and the carry adder 11 adds the one's complement of one A-bit digital value to the other A-bit digital value. A digital comparison operation is realized by determining the presence or absence of carry output to the (A+1)th bit of the addition result. Therefore, the switching point generation circuit 4 receives the lower order (nm-) of the digital code at the switching point.
1) By storing the 1's complement of the bit digital code, the comparison operation can be realized simply by using the carry adder 11.

Next, three specific examples of the code shift amount generation circuit 5 are shown in FIGS. 4, 5, and 6. In these examples, it is assumed that the smaller shift amount is stored for the area. In FIG. 4, 21 is a memory circuit, and 22 is an adder. In the memory circuit 21,
Shift amounts are sequentially stored in correspondence with signals of the upper (m+1) bits of the input code. If the data of the lower (nm-1) bits of the input code is greater than the switching point value, the adder 22 is supplied with “1” from the comparator 3, and this “1” is transferred from the terminal 1. is added to the input code. This means that
This means shifting the shift amount area by 1, and the correct corrected shift amount can be obtained from the storage circuit 21. In the opposite case, the comparator 3 outputs 0, and the shift amount of that area is obtained from the storage circuit 21.

In the example of FIG. 5, the addition operation speed in FIG. 4 is apparently eliminated to increase the speed. The code shift amount generation circuit 5 is composed of a memory circuit 31, a bus selector 32, and an adder 33 that adds 1 in advance. Here, as in the example of FIG. 4, when the comparator output is 1, the signal in which +1 is always added to the input code is selected by the input terminal A of the bus selector 32 and the memory circuit 31 is accessed. The shift amount of the next area corresponding to the input code can be obtained from the storage circuit 31. In the opposite case, input terminal B of the bus selector 32 is selected, and the shift amount corresponding to the input code is output from the storage circuit 31. In this configuration, the speed of the bus selector 32 contributes to the overall code conversion speed instead of the response speed of the adder 22 in the example of FIG. 4, but normally the operating speed of the bus selector can be reduced, so It will work faster that much.

FIG. 6 shows an example in which the response time of an adder and a memory circuit is apparently eliminated to increase the speed. It consists of a gate 44 and an adder 45 that always adds +1. Here, the top m in the input code
The bit is stored in storage circuit 42. Supplying the upper (m+1) bits in the input code to the adder 45,
Add +1 to that data, and from the addition result 1
The bits are dropped and the output of the upper m bits is obtained. This m-bit output is written into the memory circuit 41.
The exclusive OR gate 44 is supplied with the m-th bit signal from the higher order in the input code and the output of the comparator 3, and the exclusive OR gate 44 is supplied with the exclusive OR gate 44.
as a select signal. bus selector 4
The readout outputs from storage circuits 41 and 42 are supplied to the input terminals A and B of 3, respectively, and the readout output from any of them is selectively taken out according to the select signal and supplied to the adder 6.

The operation of the circuit configuration shown in FIG. 6 will be explained with reference to FIG. Figure 7 shows the relationship between the area, the correction shift amount, and the switching point when the area is equally divided by m bits of resolution of the upper DAC, and the area when it is equally divided by the resolution (m+1) bits that is twice the upper DAC. The relationship between the correction shift amount and the switching point is shown. Now, if we look at region 2 equally divided by m bits, there are two switching points, J ₂ and J ₃ , and three correction shift amounts C ₂ , C ₃ and C ₄ can be taken in that region. I understand. The switching points are identified as J ₂ and J ₃ for areas 3 and 4, which are equally divided with a resolution of (m+1), so when the code is “0” for the (m+1)th bit from the uppermost bit, the input The lower (nm-1) bits of the code are _J2
If the code is smaller than the code of the lower (nm-1) bits, it is C ₂ , and if it is larger, it is C _3. Similarly, when the code of the (m+1)th bit from the higher order is "1",
If the lower (n-m-1) bits of the input code are smaller than the code of the lower (n-m-1) bits of _J2 , then
C ₃ , or if it is larger, C ₄ . For an area equally divided by m bits, when there are two shift amounts, the larger one is stored, and when there are three, the intermediate shift amount, that is, _C3 in this case, is stored in the memory circuit 41, and the other memory circuit 42 stores the larger shift amount. The shift amount in ascending order of magnitude, in this case C ₂ , is stored. C ₃ will be stored in the next area of the storage circuit 42. Therefore, C ₃ can be identified by driving the memory circuit 41 with an m-bit signal for the input code, and C ₂ or C ₄ can be identified depending on whether the (m+1) bit value of the input code is an even number or an odd number. can be identified. Further, it is possible to identify C ₃ , C ₂ , or C ₄ depending on whether the output from the comparator 3 and the value of the (m+1) bits of the input code are even or odd. Here, whether the input code is an even number or an odd number can be determined by adding +1 and whether or not there is a carry to the next digit. For example, the output from the adder 45 that always adds +1 This can be achieved by truncating the lower 9 bits. When the number is odd, the shift amount of the next area of the storage circuit 42, ie, _C4 , can be specified in advance before the output from the comparator 3 is generated. Similarly, in the memory circuit 41, _C3 can be output before the comparator output is generated. Discrimination between C ₃ and C ₄ can be realized as shown in FIG. 6 by calculating the exclusive OR of the comparator output and the (m+1)th bit signal. In this way, in the configuration of FIG. 6, the operations of the memory circuits 41 and 42 are performed in parallel with the operation of the memory circuit 4 that outputs the switching point.
The operating speed of the entire code converter is determined by the operating speed of memory circuit 4 or whichever is slower of 41 and 42. Since the speed of the storage circuit as the switching point generation circuit 4 and the speed of these storage circuits are approximately the same, when viewed as the code shift amount generation circuit 5, the circuit configuration shown in FIG. 4 or 5 is used. In comparison, it can be seen that in the circuit configuration of FIG. 6, the speed of the memory circuit may be lowered. Furthermore, the storage capacity of each of the storage circuits 41 and 42 in FIG. 6 is 2 ^m+1 ×K (K: number of bits that can express the shift amount), as in the case of FIG. 4 or 5. .

FIG. 8 shows a specific example of a digital-to-analog converter according to the present invention, using the parts shown in detail in FIGS. 2, 3, and 6.
These parts will be shown with the same reference numerals. Here, the output of the 15-bit digital adder 6 is supplied to the original DAC 50. In the illustrated example, the original DAC 50 is an upper digit DAC (MDAC) 51 that includes a capacitor column and an analog switch, and a lower digit DAC (LDAC).
52, a reference voltage source 53, a coupling capacitor 54, and an operational amplifier 55, and an analog conversion output is taken out from an output terminal 56.

Here, set the full scale of LDAC52 to MDAC5
If the linearity is made larger than 1 LSB of 1 and the resolution of LDAC 52 satisfies the linearity, a characteristic of decreasing at the time of carry from LDAC 52 to MDAC 51 can be obtained. A jump in the negative direction occurs at the point where carry occurs from the LDAC 52 to the MDAC 51, and the characteristic curve of the LDAC 52 is superimposed with that point as the starting point. Here, by shifting the digital input using a code converter, characteristics satisfying linearity can be obtained.

In FIG. 8, the upper and lower digits of the original DAC 50 are each 8 bits, and a 15-bit DA converter is constructed by correction processing in a code converter. The DA conversion speed is determined by the sum of the speeds of the ROMs 41 and 42, the carry adder 11, the bus selector 43, the 15-bit adder 6, and the original DAC 50. For example, by normal CMOS process
When configuring the digital-to-analog converter shown in Figure 8 in the form of an LSI, the operating speeds of the above-mentioned parts are 300 to 500 ns, 100 ns, 100 ns, and 100 ns, respectively.
100ns, and the original DAC50 will be explained later, but it will be about 1 to 1.5μs, so the overall operating speed is 1.6 to 2.3μs, or about 400 to 600ksps.
(kilo samples per sec).

On the other hand, when comparing the upper bits only a few times, it is necessary to access the ROM each time the comparison is made, and the speed of such comparison operation is (100ns + 300 to 500ns) x 8 = 2.4 to 3.2 μs. When the speed of the 15-bit adder and the original DAC are added to this, the overall operating speed is approximately 3.5 to 4.8 μs, or 200 to 280 ksps. Therefore, in the example shown in FIG. 8, the speed can be increased by about twice. especially,
The improvement is even more noticeable when the ROM is slow. The speed of the original DAC is the unit capacitance of the capacitor column.
If it is 1pF, the element accuracy in that LSI is approximately
1.26%, and the error in the lower 8 bits is 0.04LSB, which fully satisfies the conditions for correction according to the present invention. The settling of the capacitor string at this time depends on the size of the switch, but it can be achieved in about 500 to 700 ns. Further, since the speed of the adder can be about 500 to 800 ns, the operating speed of the entire original DAC is about 1 to 1.5 μs.

Even when the code shift amount generating circuit shown in FIG. 4 or FIG. 5 is used, it is possible to similarly achieve a significant speed improvement.

Figure 9 shows the MDAC51 and LDAC52 mentioned above.
In this specific embodiment, 61 is a digital input signal terminal, 62 is an analog output signal terminal, and 6
3 is the terminal of the reference voltage V _ref , S _L0 , S _L1 , ......,
S _Ll-1 ; S _M0 , S _M1 , ......, S _Mn-1 is an analog switch, C ₀₀ , C _L0 , C _L1 , ......, C _Ll-1 is the lower digit side capacitance, C _M0 , C _M1 , ......, C _Mn-1 is the capacitance on the upper digit side. A capacitor array arranged with binary weights corresponding to the bits of the digital input.
1-bit LDAC52 by C ₀₀ , C _L0 ~ _{L Ll-1}
and the outputs of the m-bit MDAC 51 connected in the same way are mutually coupled by a capacitor C _c . In this circuit, if the value of the coupling capacitance C _c is equivalent to the unit capacitance of the capacitance value including the capacitance string of LDAC52 on the LSB side from the right terminal, that is, C
If _c = 2 ^l /2 ^l -1 x [unit capacity], it operates as a normal DAC with a resolution of l + m bits. This means that the output of _LDAC52 is 1/
This is because it is multiplied by 2 ^l and added to the output of MDAC51, and the analog addition of the output of MDAC51 and the output of LDAC52 is realized by the coupling capacitor C _c , and therefore the value of this capacitance C _c is the value of the LDAC52. This determines the slope of the input versus output characteristic. In other words, if the capacitance C _c is larger than 2 ^l /2 ^l -1 x [unit capacitance C ₀ ], the slope will be larger than ideal, and even if the error caused by the MDAC51 is considered, the coupling capacitance C _c must be set appropriately. For example, the change due to carry from LDAC 52 to MDAC 51 can always occur in the negative direction. Therefore, if the coupling capacitance C _c is set appropriately larger than the ideal value, that is, 2 ^l /2 ^l −1 × [unit capacitance C ₀ ], the jump in the positive direction at the joint between the outputs of the LDAC 52 and the MDAC 51 will be eliminated. . If the nonlinear error of LDAC52 is suppressed to within 1/2 LSB of the resolution of 2 ^l , and the value of capacitance C _c is set to cover the error of MDAC51, the analog output will be
There is a level at which linearity corresponding to 1LSB of DAC52 is maintained, and linearity can be satisfied by converting the digital input to the digital input of the original DAC50 that can obtain linearity.
DAC is obtained.

FIG. 10 shows an example in which the DA converter is not configured in a form divided into upper and lower parts as shown in FIG. 9, but is configured by a series of capacitance strings. Here, analog switches S _L0 , S _L1 , ......, S
_Ll-1 ; S _M0 , S _{M1 , .} capacity
C ₀₀ , C _L0 , C _L1 , ......, C _Ll-1 ; C _M0 , C _M1 ,
………,C _Mn-1 is 1.1C, respectively, as shown in the figure.
1.1C, 2.2C, ......, (1.1×2 ^l-1 ) C; 2 ^l C,
2 ^l+1 C, ......, 2 ^m+l-1 C. Capacity C ₀₀ ~
The lower digit part of C _Ll-1 corresponds to the lower DA converter,
Its full scale is, for example, (8.8C/128.8C) V _ref when l=3, and one step in the capacitance C _M0 to C _Mn-1 of the upper digit part corresponding to the upper DA converter, for example m= 4 (8C/
128.8) It is set larger than V _ref . By using the DA converter of this example in place of the MDAC 51 and LDAC 52 shown in FIG. 9, a similar DA converter can be configured.

As is clear from the above, according to the present invention, based on the digital signal of a part of the input code,
Since the code shift switching point can be made in a short time, it is possible to further increase the DA conversion speed, and to use a high-resolution and high-precision DA converter.
It can be formed in the form of LSI.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of code conversion according to the present invention, Fig. 2 is a block diagram showing the basic configuration of the code conversion circuit according to the invention, and Fig. 3 shows a specific example of the digital comparator shown in Fig. 2. block diagram,
4, 5, and 6 are block diagrams showing three specific examples of the code shift amount generating circuit, FIG. 7 is a diagram explaining the operating principle of the code shift amount generating circuit shown in FIG. 6, and FIG. The figure shows the digital
A block diagram showing a specific example of an analog converter, and FIGS. 9 and 10 are circuit diagrams showing two examples of its original DAC. 1...Digital input signal terminal, 2...Code conversion output signal terminal, 3...Digital comparator, 4
...Switching point generation circuit, 5...Code shift amount generation circuit, 6...Digital adder, 11...Carry adder, 21, 31, 41, 42...Storage circuit, 22, 33, 45... Adder, 32, 43...
...Bus selector, 44...Exclusive OR gate,
50... Former DAC, 51... MDAC, 52...
LDAC, 53... Reference voltage source, 54... Coupling capacitor, 55... Operational amplifier, 56... Analog conversion output terminal, 61... Digital input signal terminal, 6
2... Analog output signal terminal, 63... Reference voltage terminal, S _L0 , S _L1 , ......, S _Ll-1 , S _M0 , S _M
1 ,......,S _Mn-1 ...Analog switch,
C ₀₀ , C _L0 , C _L1 , ......, C _Ll-1 ; C _M0 , C _M1 ,
......, C _Mn-1 ...capacitance, C _c ...coupling capacitance.

Claims (1)

[Claims] 1. A first digital signal generating the output of the upper digits.
an analog converter, and the first output as the output of the lower digit.
Output value of 1 bit of the least significant digit digital input of the digital-to-analog converter (1LSB value)
the second, which produces a full-scale output that is always greater than
a digital-to-analog converter; and summing means for adding the output of the first digital-to-analog converter and the output of the second digital-to-analog converter to obtain an analog output signal. The digital input signal is obtained by shifting the digital input signal by a predetermined value so that the relationship between the digital input signal to the converter and the first and second digital-to-analog converters and the analog output signal is approximately linear. A digital-to-analog converter having a code converter that inputs an input code to the first and second digital-to-analog converters, wherein the code converter converts the digital-to-analog conversion characteristics of the original digital-to-analog converter. the first digital
Corresponding to each region of each digital quantity equally divided with twice the resolution of the analog converter, the point at which the shift amount in that region switches in the characteristic corrected by the code shift in the code converter is stored in advance. , a switching point generation circuit for extracting switching point data in response to a portion of the digital input signal; and digitally comparing the portion of the digital input signal and the switching point data from the switching point generation circuit. , the amount of shift within the area is 2
A comparison circuit that specifies which one to select when there are different types, and a comparison circuit that stores the shift amount if there is one type of shift within the area corresponding to the area, and stores the shift amount if there are two types. a code shift amount generation circuit that stores in advance the shift amount specified by the comparison circuit and extracts a predetermined code shift amount in response to the digital input signal; the code shift amount generation circuit and the digital input signal; A digital-to-analog converter comprising: an adder that performs digital addition of and supplies the addition result to the first and second digital-to-analog converters. 2. An original digital-to-analog converter that generates a full-scale output in the lower digit part that is always larger than the 1-bit output value (1LSB value) of the least significant digit digital input in the upper digit part, and the original digital-to-analog converter. code conversion for inputting an input code obtained by shifting the digital input signal by a predetermined value to the original digital-to-analog converter so that the relationship between the digital input signal and the analog output signal to the converter becomes almost linear; In the digital-to-analog converter having a digital-to-analog converter, the code converter divides the digital-to-analog conversion characteristics of the original digital-to-analog converter into equal parts with a resolution twice that of the original digital-to-analog converter. Corresponding to each region, the point at which the shift amount in that region switches in the characteristic corrected by the code shift in the code converter is stored in advance, and the switching point is determined in response to a part of the digital input signal. A switching point generation circuit that takes out data digitally compares a portion of the digital input signal with the switching point data from the switching point generation circuit, and determines that the amount of shift within the area is 2.
A comparison circuit that specifies which one to select when there are different types, and a comparison circuit that stores the shift amount if there is one type of shift within the area corresponding to the area, and stores the shift amount if there are two types. a code shift amount generation circuit that stores in advance the shift amount specified by the comparison circuit and extracts a predetermined code shift amount in response to the digital input signal; the code shift amount generation circuit and the digital input signal; A digital-to-analog converter comprising: an adder that performs digital addition of and supplies the addition result to the original digital-to-analog converter.