JPS5810920A - Digital-to-analog converter - Google Patents

Abstract

PURPOSE:To obtain high speed, by instantly determining a switching point from a digital signal of a part of an input code. CONSTITUTION:When a digital input code is applied to a terminal 1, a signal of high-order (m+1) bits is applied to a switching point generating circuit 4, the area is designated and when a switching point is present in the area, a signal of the low-order (n-m-1) bits is outputted, and when no switching point is present, O is outputted. A digital comparator 3 compares the code data in the low- order (n-m-1) bits in the digital input signal with an output from the circuit 4, and when the input code data is greater, a carry signal is outputted. The shift amount to be corrected corrsponding to each input code is obtained from a code shift amount generating circuit 5. The shift amount and the input code are summed with a digital adder 6, the summed output is applied to the original DC, from which an analog output corresponding to the input code is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a digital-to-analog converter (hereinafter referred to as an element DΔ0 for convenience of explanation) that has high resolution but does not satisfy accuracy, that is, does not satisfy linearity. Regarding digital-to-analog converters (hereinafter abbreviated as DAOs) that perform digital trimming to correct linearity and improve accuracy, we particularly improve the input code converter to increase the conversion speed. The present invention relates to a digital-to-analog converter.

The inventors of the present invention have proposed a DAO with digital trimming. No. j-/2723 (1) The first digital-to-analog converter that generates the output of the upper digit (
The output value for the I bit of the digital input of the lowest digit of the first digital-to-analeg converter (abbreviated as lower DAO) is the output value of the lower digit (/IJB).
The first one that produces a full-scale output that is always greater than the value of
a digital-to-analog converter and a first digital-to-analog converter;
summing means for adding the output of the analog converter and the output of the second digital-to-analog converter to obtain an analog output signal; The relationship between the digital input signal and analog output signal for this digital-to-analog converter is linear.

We have proposed a digital-to-analog converter that includes a code converter that inputs an input code obtained by shifting a digital input signal by a predetermined value to the first and λ-th digital to analog converters.

Here, the upper D^0 and the lower D^0 can be composed of the element DΔ0, and an example of the characteristics of the 3 bits of the upper DAO is shown in Figure 1, and the input from the lower D^0 to the upper D^0 The output change at the carry point always decreases.

In order to correct this characteristic to the ideal characteristic shown in Figure 1, 1
It is necessary to perform the following code conversion.

That is, when the input codes at the positions where the correction amount is switched are respectively J., Jl, Jl *.--.

When the input code is 0-J・, the shift amount is 00 (=O
), Jo″-J, then Ol, etc., and determine the shift amount from the input code.

It is necessary to add a correction amount corresponding to the shift amount to the input code.

In that case, input code J・~J1. Jl～J! .

The problem is to identify in which region the object is located. In principle, the input code is the switching point code J (1e Jl #J鵞s......
By successive comparison with Js, find the code Jq91- in which the input code is larger, and the input code is in the area J,-
1 to J. However, in the worst case, the number of times of this comparison operation is equal to the number of & switching points Jq, that is, the same number corresponding to the decomposition part of the upper DΔ0, and the above-mentioned DAO has the disadvantage of requiring a long processing time. . Yet again. The basic comparison operation can be realized by reading data indicating the switching point from the memory circuit, taking the I complement of that data, and adding it to the input code. Inversion and two addition processes are required, further increasing the processing time. The above is a major obstacle to shortening the DA conversion time of the DAO proposed above. In addition, the configuration of the logic circuit for performing such processing becomes complicated, and there is a problem in that the storage capacity of the storage circuit becomes particularly large.

Therefore, one object of the present invention is to solve the above-mentioned problems and to increase the speed of DA conversion by making it possible to immediately determine the switching point from the digital signal of a part of the input code. The object of the present invention is to provide a digital-to-analog converter that achieves the following.

In order to achieve such an object, the present invention includes a first digital-to-analog converter that generates an output of the most significant digit, and a digital input of the least significant digit of the first digital-to-analog converter as an output of the least significant digit. Output value for I bits of (t
a second digital-to-analog converter that produces a full-scale output that is always greater than the value of L8B; an original digital-to-analog converter having addition means for obtaining an analog/4G output signal, and a relationship between the digital input signal to the first and second digital-to-analog converters and the analog/4G output signal; A digital-to-analog converter comprising a food converter for inputting an input code obtained by shifting the digital input signal by a predetermined value to the first and second digital-to-analog converters so that the digital input signal is vertically integrated. In the vessel.

The code converter is.

Corresponding to each area of each digital quantity obtained by equally dividing the digital-to-analog conversion characteristics of the original digital-to-analog converter with twice the resolution of the digital-to-analog converter of jI/, A switching point generation circuit that stores in advance a point at which the shift amount in that region in a characteristic corrected by code shift switches, and extracts data at the switching point in response to a part of the digital input signal marked with #.

A part of the digital input signal is digitally compared with data of the switching point from the switching point generation circuit, and when there are several types of shift amounts within the area, specifying which one to select. Comparison circuit.

Corresponding to the area, there is a shift amount within that area.

If it is 7811m, the shift amount is memorized, and if there are two types, the shift amount specified by the comparison circuit is stored in advance, and the code shift amount is used to extract a predetermined code shift amount in response to the digital input signal. generation circuit.

The present invention is characterized by comprising an adder that performs digital addition of the code shift amount generation circuit and the digital input signal and supplies the addition result to the first and second digital-to-analog converters.

Another aspect of the present invention is an original digital-to-analog converter that generates a full-scale output in the lower digit part that is always larger than the output value (tL8B value) for 1 bits of the least significant digit digital input in the upper digit part.

The input code obtained by shifting the #b digital input hexagonal signal by the necessary value so that the relationship between the digital input signal and the analog output signal to the original digital-to-analog converter is almost linear is converted to m era. and a code converter input to the digital-to-analog converter.

The code converter is.

Digital/7f of the original digital to analog converter
Corresponding to each area of each digital quantity obtained by dividing the O-g conversion characteristic into equal parts with the resolution multiplied by that of the original digital-to-analog converter, A switching point generation circuit that stores in advance a point at which a shift amount changes and extracts data at the switching point in response to a part of the digital human input signal.

A part of the digital human input signal is digitally compared with data of the switching point from the switching point generation circuit, and when there is one type of shift amount within the area, specifying which one to select. Comparison circuit.

Corresponding to the area, there is a shift amount within that area.

If there is one type, the shift amount is stored, and if there is one type, the shift amount specified by the comparison circuit is stored in advance, and a predetermined code shift amount is extracted in response to the digital input signal. quantity generating circuit.

The code shift amount generating circuit and the digital input signal described in III are digitally added, and the present invention will be described in detail below with reference to the drawings.

FIG. 2 shows an embodiment of the basic configuration of the code converter in the digital-to-analog converter of the present invention, where l is the digital signal terminal, ko is the code conversion output signal terminal to the source DΔ0, and 3 is the code conversion output signal terminal. 41+ is a switching point generation circuit, j is a code shift amount generation circuit, and t is a digital adder.

To explain the circuit operation, the number of bits of the one-dimensional DAO is n bits, the number of bits of the upper DAO is m bits, and the number of bits of the lower DAO is
Let the number of bits be j2 nm bits. Furthermore, if the number of bits after correction is k, it is clear that the number of bits after correction is smaller than before correction, k<n. Each area shown in Fig. 1.

Twice the resolution of the upper DAO in the original D^0 (
Since this corresponds to m+1) resolution, that is, the signal gap in the upper (m+/) bits of the input code can be identified. Therefore, as shown in figure #IIE1, the upper order of the input code (m+
/) Corresponding to the bit signal, the switching point generation circuit 1 For example, ROM 4CgJ switching point code J
The signal of the lower [n-(rn+/)] bip in s I Jl m'*e ``-''・ is memorized. If there is no switching point in that area, O is stored.

Similarly, in response to the signal of the upper (m+/) bits of the input code, a code shift amount generating circuit! The shift amount 00 ``'' e CI Ho, l-... of that area is stored in advance.

When a digital input code is applied to terminal l.

The signal of the upper (m+/) bits is supplied to the switching point generation circuit, and the frR castle is specified from it.

The switching point generating circuit outputs a signal of the lower (m-rm-t) bits if there is a busy switching point in that area, and outputs 0 if there is no switching point in that area. Digital comparator J compares the code data of the lower (*-m-t) bits in the digital input signal with the output from the switching point generation circuit, and if the input code data is larger, it outputs a carry signal. Output. That is, when a switching point exists within that region, since there are two types of shift amounts within that region, it is possible to determine which of the two shift amounts to use by this comparison operation. Assuming that the smaller of the two shift amounts is stored in the code shift amount generating circuit 5 in correspondence with that area, when the input code is small, the shift amount is stored in the next area, and when the input code is large, the shift amount is stored in the next area. The code shift amount generation circuit is driven to output the corresponding shift amount. Conversely, if the larger of the two shift amounts is stored in the code shift generator circuit j [for that area, then when the input code is large, the shift amount corresponding to that area is stored.

When it is small, the code shift amount generation circuit generates the shift amount of the previous area! The shift amount to be corrected corresponding to each input code can be obtained from the code shift amount generating circuit 1 by the operation of 0 or more by driving . Finally, the shift amount and the input code are added by the digital adder 6, and the added output is supplied to a one-dimensional DAO (not shown) as an input code corrected according to the input code.

From this originator 0, an analog output that correctly corresponds to the input code is obtained. Note that in the input box addition 64, addition is performed such that the most significant digits match.

FIG. 1 shows a specific circuit example of the digital comparison WhJ, where // is a carry adder from which only a carry signal is output. The switching point generating circuit DA of this example is constituted by a memory circuit that stores the complement of I, and the one-digit up adder // adds the complement of l of one M bit digital value to the digital value of the other A bit.

A digital comparison operation is realized by determining whether or not there is a carry output to the (A0/)th bit of the addition result. Therefore, by storing the complement of I of the digital code of the lower (m-m-/) bits of the digital code at the switching point in the switching point generation circuit, it is possible to simply use the carry adder/l. Comparison operation can be realized.

Next, three specific examples of the code shift amount generation circuit S0 are shown in Figs. As shown in FIG. In these examples, it is assumed that the smaller shift amount is stored for the area. 9
In Figure 411, l is a storage circuit and n is an adder.

The storage circuit 1 sequentially stores shift amounts corresponding to the signals of the upper (m+/) bits of the input code. If the data at the lower (n-m-/) bits of the input code is greater than the switching point value, the adder n is supplied with 11" from the comparator 3, and this @l" is supplied from the terminal I. is added to the input code. This means that the shift amount area is shifted by I, and the correct corrected shift amount can be obtained from the storage circuit 1. In the opposite case, the comparator J outputs Q, and the shift (quantity) of that area is obtained from the storage circuit 1.

In the example shown in FIG. 5, the addition operation speed in FIG. 1 is apparently eliminated to increase the speed. This code shift amount generation circuit! is composed of a memory circuit J/, a path selector n, and an adder 33 that adds l in advance. Here, as in the example in Figure $44, if the comparator output is l, the signal in which +l is always added to the input code is sent to the bus selector n.
This is because the memory circuit 31 is accessed by selecting the input terminal A of the memory circuit 31.

In the case of at', the memory circuit J/KAMO can obtain the shift amount of the next area corresponding to the input code.

Input terminal B of bus selector n is selected, and the storage circuit 31 also outputs the shift amount corresponding to the input code. In this configuration, the speed of the bus selector 32 contributes to the overall code conversion speed instead of the response speed of the addition WIn in the example shown in Figure 1, but normally the operating speed of the bus selector can be reduced, so It will work faster that much.

Figure 5 shows an example of speeding up the response time of the adder and memory circuit by seemingly eliminating it, and this code shift amount generation circuit! are two memory circuits q-Jqs and q, a bus selector Q, and an exclusive OR gate.

and an adder peg that always adds ten/.

Here, the upper m bits of the input code are stored in storage direction -p. The upper (m+l) bits in the input code are supplied to the adder nail, 10 I is added to the data, and l big 4 digits are dropped from the addition result to obtain the output of the upper m bits. This m-bit output is written into the memory circuit V. For the exclusive OR signal, the m-th bit signal from the most significant bit in the input code and the output of the comparator J are supplied, and the exclusive OR output is supplied to the bus selector R as a selection signal. Input terminals M and BK of the bus selector q supply successive outputs from the memory circuits V and 2, respectively, and selectively take out the successive output from either according to the select signal and supply it to the adder t. .

The operation of the circuit configuration shown in tR1 will be explained with reference to FIG. Figure 7 shows the relationship between the area, the correction shift amount, and the switching point when the upper D^0 is equally divided by m bits of resolution, and the relationship between the area and the switching point when the upper D^0 is divided equally by the resolution (m+/) bits of the upper DAO. The relationship between the area when divided, the corrected shift amount, and the switching point is shown. now.

Let's take a look at the area divided equally by 臘bits.

There are two switching points, J8 and Jl, and three correction shift amounts of 0. , o, and C4. The switching points are identified as J and J for areas 3 and 3, which are equally divided with a resolution of Cm+/). Therefore, when the code @O" is the (m+/)th bit from the high-order, Lower input code (!1-IXI-/
) bit is smaller than the code of the 13 lower (n-m-/) bits, then C! , if it is larger, it becomes Cs, and if the code I code of the (m+/)th bit from the higher order is "l", the lower (n-m-/) bits of the input code are the lower (n-m- /) Os if it is smaller than the bit code
, if it is larger, it may be set to C4.

For a region equally divided by m bits, when the shift amount is λ, the larger one is used, and when there are three, the intermediate shift amount is used.

That is, in this case, am is stored in the storage circuit f/.

The other memory circuit stores shift amounts in ascending order, in this case CI. When Cs is stored in the next area of the storage circuit p, it becomes K. Therefore.

With respect to the input code, it is possible to identify whether the memory circuit is IO or 04 using an m-bit signal. Further, it is possible to identify whether the value is 03 or o=+04 depending on whether the output from the comparator J and the value of the (m+/) bits of the input code are even or odd. Here, whether the input code is even or odd can be determined by adding +/ and whether there is a carry to the next digit.1For example, the output from an adder that always adds +l This can be achieved by truncating the lower two bits of . When the number is odd, the shift amount of the next area of the storage circuits, ie, 04, can be specified in advance before the output from the comparator J is generated. Similarly, in the memory circuit 117, 03 can be output before the comparator output is generated. Identification between Os and 04 can be made using the comparator output and (
By performing an exclusive OR with the m+/)th bit signal, the second bit can be realized as shown in the figure. In this way, in the configuration shown in Fig. 1, the operations of the memory circuits V and P are performed in parallel with the operation of the memory circuit reference that outputs the switching point, so the operation speed of the entire code converter depends on the memory circuit structure. Or, it is determined by the slower operating speed of either #l or #l. Since the speed of the memory circuit used as a switching point generation circuit and the speed of these memory circuits are about the same, the code shift amount generation circuit!
When viewed as follows, it can be seen that the speed of the storage circuit can be lowered in the circuit configuration shown in FIG. 5 compared to the one-way configuration shown in FIG. The storage capacities of the storage circuits V and ξ in FIG. 4 are the same as those in FIG. 5 or FIG.

(Ill+' x x c x , the number of bits that can express the shift amount).

FIG. 1 shows a specific example of a digital-to-analog converter according to the present invention, in which each part shown in detail in FIGS. 2, 3, and 4 is used.

These parts will be shown with the same reference numerals.

Here, the output of the lj-bit digital adder base is expressed as element D
^0 Supply to jo. The former DAO10 is shown in the illustrated example.

Upper digit DAO (MDA) including capacitor column and analog switch
O) jt/, lower digit D^O (LDAO) jJ, reference voltage source j3, coupling capacitor Ha, and operational amplifier! ! and has.

Output terminal! Extract the analog/4G conversion output from 6.

Here, the full scale of LDAOjJ is MDACjl
/ If it is larger than 18B and satisfies its linearity at LD^0!20 resolution, MD from LDAOjJ
A characteristic that decreases upon carry in ACjl is obtained.

A jump in the negative direction occurs at the point where the carry from LDAOjJ to MDAOst occurs, and LDΔOj starts from that point.
This is a superposition of the characteristic curves of here.

By shifting the digital input using a code converter, characteristics satisfying linearity can be obtained.

In the figure, the upper and lower digits of the element DΔ0!0 are each r bits, and a /J-bit DΔ converter is constructed by correction processing in a code converter.

The conversion speed is determined by the sum of the speeds of R2M17 and p1 carry adder //, path selector IJ, /J bit adder 6, and original DAO 10, for example.

When the digital-to-analog converter shown in the figure is configured in the form of L8I using a normal 0MO87a process, the operating speed of each of the above-mentioned parts is 300~! 00 m
s, 100ns, 100mm, 100
mm, and the original value will be explained later, but since it is approximately /-1,jμ, the overall operating speed is t6 to 23μS.

That is, about 800 to 400 kgpm (kilo s
ampl@s p@r se@) can be realized.

On the other hand, when comparing the upper bits only several times, it is necessary to access the ROM each time the comparison is made, and the speed of such comparison operation is (io).

t's +JOO~! 00 mis ) X I #
2.44 ~ λμS.

With the addition of the K/j bit adder and the speed of the element D^0, the overall operating speed is approximately! j −@rμS, i.e. 2
00~ko II kspm. Therefore, in the example of the tlpJt diagram, it is possible to achieve about twice the speed. In particular, R
The improvement is even more pronounced when the OM speed is slow.

Assuming that the unit capacitance of the capacitor array is /pp, the speed of the element D^0 is approximately /21. %, and the error of the lower r bits is 0. Since it is OQ L8B, it fully satisfies the conditions for correction according to the present invention.

The setting ring of the capacitor string at this time depends on the size of the switch, but is approximately ! Approximately OO to 700 ns can be achieved.

Also, since the speed of the adder can be achieved on the order of 100-10 On+s, the operating speed of the 1-element DAO as a whole is approximately I~//
, about 74 seconds.

Even when using the code shift amount generating circuit shown in FIG. 1 or FIG. 1, it is possible to similarly achieve a significant speed improvement.

Figure 2 shows the MDAO! / and a specific embodiment of the LDAO 12, At is a digital input signal terminal, 6 is an analog output signal terminal, and t3 is a reference voltage V.
rd terminal h SLO+ 8Ll t ”' + 'L
j-1; 8Ml) m8M1+...+ 'Ml! l-1
is anapgusuitte h 00C++ 'Lee'LI
I"' * 0Lj-1 is the lower digit side capacity, 1010Mo
1O+1+#0Mm-1 is the capacitance on the upper digit side. Capacitance array ooo e 0L (1”-0Lj-1) arranged with binary weights corresponding to digital input bits! Output of LDAOjJ of bits and MDAO of m bits connected in the same way!-/ are mutually coupled by a capacitor c6.In this circuit, the value of the coupling capacitor ocl is
From the right terminal, a capacitor array of LSI-based LDAOjJ is combined to operate as a normal DAO with apparent resolution.

This means that the output of LDAOjJ has a coupling capacitance of 0. 5 from K
4 (this is because it is multiplied and added to the output of MDAOjJ.

Analog addition of the output of Gogo a Zt and the output of LD^Oj2 is realized by a coupling capacitor of 0°, and therefore the value of this capacitance C,, is larger than the ideal input-to-output characteristic of LD^OI. Therefore, the coupling capacitance Cc must be set appropriately even if the error caused by the MD module oji is taken into consideration.

Always LD^0! MDAO from Ko! If the change amount due to carry to / is set appropriately larger than 0 (+), LDACz
There will be no jump in the positive direction at the joint between the outputs of LDAO and MDAO1/, and the nonlinear error of LDAO and MDAO will be suppressed to within 21% L8B of the resolution, and MDAO! If the value of capacitance Cc is set to cover the error of /, there will be a level in the analog output that maintains the linearity corresponding to /L8B of LDACjJ, and linearity can be obtained from the digital input. When converted to the digital input of the original DAO 30, the DA that satisfies the iI form property is obtained from k.
0 is obtained.

In Fig. 70, the D^ converter is not constructed in a form divided into upper and lower parts as shown in Fig. 2, but by a series of capacitance strings.
^ An example of configuring a converter is shown. Here, analog switch 8LOe 8L1y ”-e 5Lj-1; 8MO+
8M1 e ''' * 5Mm-1 is the case of Fig. 9.
CLOe CLl r"' e 0LJ-1: OM
I e OMI * ”' s 0Mm-1 is as shown in the diagram, tO, 1, to, x20.--,
(ttxa)0;ko'0. Koj+1. ＋＊・・・
・, IO can be added. The lower digit part of the capacitance 000 to 0Lj-1 corresponds to the lower DΔ converter, and its full scale is 1, for example! -3 when K Ct,tO//2t10)V
,. f, and l steps in the capacitance CM0 to 0 Mm-1 of the upper digit part corresponding to the upper DA converter, for example, <ro7/Jffr) Vref when m = 44.
It is determined to be larger. The DA converter of this example is the hDAOzt and LDAO! shown in the IRP diagram. By using this instead of the above, a similar DA converter can be configured.

As is clear from the above, one aspect of the present invention is based on a digital signal of a portion of an input code.

Since the code shift switching point can be made in a short time, the D-conversion speed can be further increased.

Furthermore, a high-resolution and high-precision DA converter can be formed in the form of 18I.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram of the principle of code conversion according to the present invention;
The figure shows the basic configuration of the code conversion circuit according to the present invention. Figure, No. JfIA is #! A block aS shows a specific example of the digital comparator shown in FIG. WI4#, FIG. 1, and FIG. 4 are block diagrams showing three specific examples of code shift amount generation circuits, respectively. FIG. 7 is an explanatory diagram of the operating principle of the code shift amount generating circuit shown in FIG. 11I4, FIG.
Each figure is a circuit diagram showing an example of the element DΔ0. l...Digital input signal terminal. λ...Code conversion output signal terminal. 3...Digital comparator, reference switching point generation circuit. 5...Code shift amount generation circuit. 6...Digital adder, U-: Carry adder. 2/, J/, u, ξ--Storage circuit, 22. JJ, jiS- adder. JJ, 〃・-Pass Ryuushikta, *-@other disjunction gate. jO...former DAO! /-Sukedoro C1 j2-LDmu0. ! ! -Reference voltage source. Za: Coupling capacitor, jj: Operational amplifier. jj... Analog conversion output terminal. 6/...Digital input signal terminal, 6...Analog output signal terminal. 63...Reference voltage terminal, SLO+ 'ILI e ''' + 8LJ-1+ 8
MoI'Ml + "'#'Mm-1 analogue switch. 000 + 0L(1*O,,1#...+0Lj-1
; OMO* CMl w ”' w CMm-1...
·capacity. Cc...Coupling capacitance. Patent applicant Nippon Telegraph and Telephone Public Corporation Figure 112

Claims (1)

[Scope of Claims] 1) A first digital-to-analog converter that generates an output of the most significant digit, and a l-pitch of the digital input of the least significant digit of the first digital-to-analog converter as an output of the least significant digit; a second digital-to-analog converter that generates a full-scale output that is always greater than the output value of /L8B, and the output of the first digital-to-analog converter and the second digital-to-analog converter; a digital input signal for the first and first digital to analog converters and a digital input signal for the first digital to analog converter and a summing means for obtaining an analog output signal. The input code obtained by shifting the digital input signal by a predetermined value so that the relationship between the first and I! In a digital-to-analog converter having a code converter input to a digital-to-analog converter. The above-mentioned; - code converter is. Corresponding to each area of each digital quantity obtained by equally dividing the digital-to-analog conversion characteristic of the original digital-to-analog converter with a resolution twice that of the first digital-to-analog converter. a switching point generation circuit that stores in advance a point at which the shift amount in the region in the characteristic corrected by the code shift in the code converter switches, and extracts data at the switching point in response to a part of the digital input signal; . A part of the digital input signal is digitally compared with data of the switching point from the switching point generation circuit described in #I, and when there are two types of shift amounts within the area, which of them is selected is determined. and the specified comparison circuit. Corresponding to the area, if there is one type of shift amount in that area, that shift amount is stored, and if there are two types, the shift amount specified by the comparison circuit is stored in advance, and the digital A code shift amount generation circuit that extracts a predetermined code shift amount in response to an input signal. A digital converter comprising: an adder that performs digital addition of the code shift amount generation circuit and the digital input signal and supplies the addition result to the first/second digital/analog converter. analog converter. 2) l of the digital input of the least significant digit in the upper digit part
An original digital converter that generates a full-scale output of the lower digits that is always larger than the bit output value (/L8B value).
with an analog converter. The digital input signal is shifted by a predetermined value so that the relationship between the digital input signal and the analog output signal for the original digital to analog converter is approximately linear. and a code converter input to the analog converter. The code converter is. The digital-to-analeg converter characteristics of the original digital-to-analeg converter are
Corresponding to each region of each digital quantity equally divided by twice the resolution, the point at which the shift amount in that region switches in the characteristic corrected by the code shift in the code converter is stored in advance, and the digital input signal is and a switching point generation circuit that extracts switching point data in response to a portion of the switching point. A part of the digital input signal and the switching point data from the switching point generation circuit are digitally compared, and if there are two types of shift amounts within the area, it is determined which one to select. Comparison circuit. Corresponding to the area, the shift amount within the area is 71 m.
If it is like that, memorize the shift amount. If there are two types, a code shift amount generating circuit memorizes in advance the shift amount specified by the comparison circuit and extracts a predetermined code shift amount in response to the digital input signal. Perform digital addition of the code shift amount generation circuit and the digital input signal; 1. and an adder that supplies the addition result to the original digital to analog converter? Characteristic digital/analog converter.