JP3501701B2 - D / A converter device and D / A conversion method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention converts a digital signal into an analog signal D / A converter device and D
/ A conversion method .

[0002]

2. Description of the Related Art As a conventional R2R voltage addition type D / A converter device, a circuit as shown in FIG. 3 is used. FIG. 3 shows a 9-bit input D / A converter device. This D / A converter device converts 9-bit digital signals (D0 to D8) into D flip-flops (hereinafter simply referred to as flip-flops) FFC0 to FF.
The holding circuit 32 made up of C8 converts the signals into digital signals (a0 to a8) synchronized with the clock CLK,
A 9-bit digital signal (D0 to D0) is added via a bit signal line 33 to a resistance ladder circuit 31 which is a resistance division circuit combining two types of resistance elements R and 2R.
This is a configuration for obtaining an analog signal output corresponding to D8).

FIG. 4 shows a conventional resistance voltage dividing type D / A converter device. In this D / A converter device, as shown in FIG. 4, a resistance element group 41 composed of unit resistance elements R0 to R511 connected in series and to which a reference voltage VR is applied, and connection of each of the unit resistance elements R0 to R511. It is composed of a switch circuit 42 which selects and outputs either one of a point potential and a ground potential, and a decoder 43 which controls ON / OFF of the switch circuit 42 based on a 9-bit digital signal (D0 to D8). .

In this D / A converter device, a divided voltage of the required number of codes is created by connecting unit resistance elements R0 to R511 in series, and a decoder 43 outputs a 9-bit digital signal (D0 to D8). By decoding and selecting one divided voltage in the switch circuit 42 according to the output of the decoder 43, a 9-bit digital signal (D0 to D
An analog output signal corresponding to 8) is obtained.

The above-mentioned R2R voltage addition type D / A converter device can reduce the number of resistance elements as compared with the above resistance voltage dividing type D / A converter device shown in FIG.
There is an advantage that the D / A converter device can be formed in a small area.

On the other hand, the resistance voltage dividing type D / A converter device requires a large number of unit resistance elements R0 to R511, but the principle of differential linearity is the most important characteristic for the D / A converter device. Has the advantage of being guaranteed. The differential linearity is 1 of the digital input value.
It is the characteristic that the analog signal output always increases and does not decrease with an increase in the code (digital value).

[0007]

As described above,
In the conventional D / A converter device, a large number of unit resistance elements R0 to R511 are required in the case of the resistance voltage dividing type shown in FIG. Have.

Further, in the case of the R2R voltage addition type shown in FIG. 3, the occupied area on the chip when it is made into a semiconductor can be formed relatively small. However, there is a problem that the differential linearity largely depends on the relative accuracy between the resistance elements, and in particular, the relative accuracy between the resistance elements greatly affects the differential linearity with respect to the change of MSB (most significant bit).

A D / A converter device capable of solving this difficulty is proposed in Japanese Patent Laid-Open No. 4-330827. As shown in FIG. 5, this D / A converter device includes inverters IN0 to IN9 for inverting 9-bit digital signals (D0 to D8) and a NAND circuit NAN.
The logic circuit 53 includes 0 to NAN7 and NOR circuits NOR0 to NOR7, and resistance ladder circuits 51 and 52. Then, an analog signal output corresponding to the 9-bit digital signal (D0 to D8) is obtained as a parallel composite output of the resistance ladder circuits 51 and 52.

In this D / A converter device, when the MSB (D8) of the 9-bit digital signal (D0 to D8) is "1", the reference point A is supplied with the potential (power supply potential) of "1". In the 8-bit resistance ladder circuit 51, the potential "1" (power supply potential as the output of the NAND circuits NAN0 to NAN7) is applied to the resistance elements 2R corresponding to all the bits. As a result, the 8-bit resistance ladder circuit 51 becomes equivalent to the resistance element 2R connected between the potential of "1" (power supply potential) and the output terminal.

To the 8-bit resistance ladder circuit 52, a potential "1" (power supply potential as the output of the inverter IN9) is applied to the reference point B, and an 8-bit digital signal (D7 to D0) other than MSB is supplied. Depending on the level, the resistance element 2R of each bit has a potential of "1" (NOR circuits NOR0 to NO
Power supply potential as output of R7) or potential of "0" (N
Ground potential as output of OR circuits NOR0 to NOR7)
Will be given selectively.

Therefore, the 8-bit resistance ladder circuit 5
By connecting the output ends of 1, 52 in common, the combined circuit of the 8-bit resistance ladder circuits 51, 52 is a 9-bit resistance ladder in which the resistance element 2R corresponding to the MSB is given a potential of "1". An analog signal output corresponding to a 9-bit digital signal (D0 to D8) whose MSB is "1" is obtained.

A 9-bit digital signal (D0-D0)
When the MSB (D8) of D8) is "0", the reference point B
In the 8-bit resistance ladder circuit 52 to which the potential of “0” (ground potential as the output of the inverter IN9) is applied to, the potential of “0” (NOR circuits NOR0 to NOR7) is applied to the resistance elements 2R corresponding to all the bits. Ground potential) as the output of the. As a result, the 8-bit resistance ladder circuit 52 becomes equivalent to the resistance element 2R connected between the potential of "0" (ground potential) and the output terminal.

The 8-bit resistance ladder circuit 51 is supplied with a potential (power supply potential) of "1" at the reference point A, and each bit is supplied in accordance with the level of an 8-bit digital signal (D7 to D0) other than MSB. "1" potential (NA
Power supply potential as output of ND circuits NAN0 to NAN7)
Alternatively, the potential of "0" (NAND circuits NAN0 to NAN7
The ground potential) is selectively supplied as the output.

Therefore, the 8-bit resistance ladder circuit 5
By connecting the output terminals of 1, 52 in common, the synthesis circuit of the 8-bit resistance ladder circuits 51, 52 is a 9-bit resistance ladder in which the potential of "0" is applied to the resistance element 2R corresponding to the MSB. An analog signal output corresponding to a 9-bit digital signal (D0 to D8) whose MSB is "0" is obtained, which is equivalent to the circuit.

However, in the D / A converter device shown in FIG. 5, the inverter IN9 is connected to the reference point B. There is an inevitable resistance component between the input and output of the inverter. Therefore, when D8 is "0", the value of the reference point B is "0" and the potential at the point C is 2R and the inverter I.
The potential difference determined by the resistance partial pressure of the resistance component of N9 increases from "0". The value of the reference point B when the D8 is "1" drops from by the potential difference which is determined "1" and the potential of the point C by the resistance partial pressure of the resistance component of the 2R and the inverter I N9 "1". Further, the potential at the point C is “0” of D0 to D7,
It changes according to the value of "1". Therefore, there is a problem that the change of the analog signal output of the resistance ladder circuit 52 with respect to the change of the input digital signals (D0 to D8) is irregular.

Now, the reference point will be described. In general, when two different potentials are divided into 2 N powers, the possible division potentials are 2 N + 1 when the potentials at both ends are included.
Exist individually. However, the value that the N-bit D / A converter can take is 2 N powers. R2R resistance ladder type D /
In case of A converter, 2R which is the resistance of this "reference point"
If "0" is connected to, it becomes a circuit that outputs 2 N powers from the lower end potential, and if "1" is connected, it becomes 2 N from the upper end potential.
It becomes a circuit that outputs the power of two, and if any other value between "0" and " 1 " is connected, the internal measurement is divided by the Nth power of 2 by the potential difference corresponding to that arbitrary value from both ends. It is described as a "reference point" because it is a circuit that outputs the power of two.

Further, due to such a difference in structure among a plurality of resistance ladder circuits to be combined, not only a simple repetitive configuration is impossible, but also a logic circuit which supplies an output to these resistance ladder circuits. However, there is a problem that it becomes complicated especially when four or more resistance ladder circuits are combined.

An object of the present invention is to have a D / A having the same structure.
An object of the present invention is to provide a D / A converter device that can realize good differential linearity with a simple repeating configuration of a converter unit.

Another object of the present invention is to provide a D / A converter device which occupies a relatively small area on the chip.

[0021]

A D / A converter device according to claim 1 of the present invention is a D / A converter device for converting an input digital signal into an analog signal, wherein (M + N) bits (here , Where M and N are positive integers) , and the MSB side M bit "0", "1"
And N-bit digital signal all in accordance with the value "0", and the number (M power minus 2) by combining the N-bit digital signal are all "1", LSB side of the digital signal "0" of the N bits, "1" value and a decoder for converting the same N-bit digital signal into one and the digital signal of N bits M-th power of two which is the output of the <br/> decoder of converting an analog signal to each M-th power of two, and a N-bit D / a converter unit having a potential source of exactly the same configuration of the circuit connection and the reference point. Then, the a R2R voltage addition-type composed of N-bit D / A converter unit resistor ladder circuit, an analog signal output of the N-bit D / A converter unit having the identical structure of the second M-th power To the terminal
Connect one end of each resistor individually and two other ends of the resistor
Is connected as a unit, and if there is only one connection, M + N
Output as an analog signal with bit resolution
If there are a plurality of
Connect one end of each resistor individually and connect the other end of this new resistor to 2
Connect this in units and connect directly from this connection or this connection
And outputs as an analog signal with M + N bit resolution.

According to this configuration, the decoder (M + N)
Bit (M and N are positive integers) digital signal of 2 M
To convert N M-bit digital signals to 2 M power, and 2 M N-bit digital signals to M analog power are respectively converted into analog signals by the N-bit D / A converter unit having the same configuration. The analog signal outputs of the M-th power of 2 N-bit D / A converter units are connected in parallel via resistors, respectively, and combined to output as an analog signal of M + N-bit resolution.

In this D / A converter device, D / A conversion can be realized by a simple repeating structure of D / A converter units having the same structure, and good differential linearity can be realized. Further, since the N-bit D / A converter unit is the R2R voltage addition type configured by the resistance ladder circuit, the occupied area on the chip can be made relatively small. The present invention
The D / A conversion method according to claim 2, wherein the input digit
A D / A conversion method for converting a digital signal into an analog signal
, (M + N) bits (where M and N are positive integers)
Of the digital signal of "0" of M bits on the MSB side,
N-bit digit that is all "0" according to the value of "1"
Tal signal and N-bit digital signal that is all "1"
And (2 M-1), and the digital
Same as the value of "0" or "1" of N bits on the LSB side of the signal
Decoder hand to convert N-bit digital signal into one
Stages, and the M-th power of 2 N-bits output from the decoder means.
Convert each digital signal to an analog signal
2 M powers of circuit connections and reference point potential sources
N-bit D / A converter unit having the same configuration
And means. The N-bit D / A converter
R2 in which the barter unit means is composed of a resistance ladder circuit
R voltage addition type conversion means, wherein the M power of 2
N-bit D / A converter unit having exactly the same configuration
Connect one end of the resistor individually to the analog signal output terminal of the
And connect the other end of the resistor in units of 2
Analog with M + N bit resolution when there is only one part
Output as a signal, and if there are multiple connections,
Connect one end of a new resistor individually to multiple connections
Then connect the other end of this new resistor in units of 2
M + N bits directly from the connection or via this connection.
Output as an analog signal with high resolution.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described with reference to the drawings.

[First Embodiment] FIG. 1 is a circuit diagram showing a first embodiment of a D / A converter device according to the present invention. Hereinafter, a case where M = 1 and N = 8 will be described.

This D / A converter device converts an input digital signal into an analog signal,
As shown in FIG. 1, a 9-bit digital signal (D0 to D0
D8) as two 8-bit digital signals (a0-A)
7) and (b0 to b7), and a decoder 100 that converts each of the two 8-bit digital signals (a0 to A7) and (b0 to b7) output from the decoder 100 into an analog signal. Resistor ladder circuit as N-bit D / A converter unit having exactly the same configuration
1 and 12 are provided.

Then, the analog signal outputs of the two resistance ladder circuits 11 and 12 having exactly the same structure are connected in parallel via the resistance element R and combined to output an analog signal of 9-bit resolution.

A more specific description will be given below.

The decoder 100 receives the 9-bit digital signal (D0 to D8) and the clock CLK, and
Bit digital signal (D0 to D8)
Two 8-bit digital signals (a0
~ A7), (b0 to b7).

Therefore, the decoder 100 includes 16 switch D flip-flops (hereinafter, simply referred to as switch flip-flops) FFSA0 to FFSA7, F.
It is composed of FSB0 to FFSB7 and an inverter IN11.

Then, a 9-bit digital signal (D0
Of 8-bit digital signal (D0 to D8)
7) is a flip-flop with switch FFSA0 to FFS
The data input terminals D of A7, FFSB0 to FFSB7 are input.

A 1-bit digital signal (D8)
Flip-flops with switches FFSA0 to FFSA7
Of the flip-flops FFSB0 to FF with switch, which are input to the respective switch input terminals SW of 1 to and are inverted by the inverter IN11 from the 1-bit digital signal (D8).
It is input to each switch input terminal SW of SB7.

Further, the power supply voltage is the data input terminal D of each of the flip-flops FFSA0 to FFSA7 with a switch.
T is commonly input to T, the ground voltage is commonly input to each data input terminal DT of the flip-flops FFSB0 to FFSB7 with switches, and the clock CLK is flip-flops FFSA0 to FFSA7 and FFSB0 to FFSB with switches.
It is input to each clock terminal CK of FFSB7.

Further, a flip-flop with switch FFS
An 8-bit digital signal (a0-a7) from each output terminal Q of A0-FFSA7 is an 8-bit signal line 1
3 is input to the resistance ladder circuit 11. Similarly,
An 8-bit digital signal (b from the output terminal Q of each of the flip-flops FSBFO to FFSB7 with switch)
0 to b7) are input to the resistance ladder circuit 12 via the 8-bit signal line 14.

That is, in the decoder 100, the MSB (D8) of the 9-bit digital signal (D0 to D8) is "0".
When, the 8-bit digital signal (a0 to a7)
As an 8-bit digital signal (D0 to
D7) is output and an 8-bit digital signal (b0 to b
All of "0" is output as 7). Also, the MSB (D8) of the 9-bit digital signal (D0 to D8) is "1".
In case of, 8-bit digital signal (b0 to b7)
As an 8-bit digital signal (D0 to
D7) and outputs an 8-bit digital signal (a0-a
All of "1" is output as 7).

The resistance ladder circuits 11 and 12 include a resistance element R.
And a resistance element 2R are combined to have the same structure, and an 8-bit digital signal (a0 to A7),
Each of (b0 to b7) is converted into an analog signal. The output terminals of the resistance ladder circuits 11 and 12 are connected in parallel via the resistance element R, and the respective analog signals are combined.

As described above, the 8-bit digital signal (a0 to a7) from the output terminal Q of the flip-flops with switches FFSA0 to FFSA7 in the decoder 100 is input to the resistance ladder circuit 11. When the 1-bit D8 (MSB) of the digital input signals (D0 to D8) connected to the switch input terminals SW of the flip-flops with switches FFSA0 to FFSA7 is "0", the flip-flops with switch FFSA
Digital input signals L0 (LSB) to D7 input to the data input terminals D of 0 to FFSA7 are selected as 8-bit digital signals (a0 to a7).

Digital input signals (D0 to D8)
When the 1-bit D8 (MSB) is "1", the power source (digital signal "1") input to the data input terminal DT of the flip-flops with switches FFSA0 to FFSA7 is an 8-bit digital signal (a0 to a0). a7)
Is selected as. Then, the selected 8-bit digital signal (a0 to a7) is input to the resistance ladder circuit 11 in synchronization with the synchronization clock CLK input to the clock terminal CK.

As described above, the 8-bit digital signal (b0 to b7) from the output terminal Q of the flip-flops with switches FFSB0 to FFSB7 in the decoder 100 is input to the other resistance ladder circuit 12. When the 1-bit D8 (MSB) of the digital input signals (D0 to D8) connected to the switch input terminals SW of the flip-flops with switches FFSB0 to FFSB7 is "1", the flip-flop with switches FFSB
Digital input signals L0 (LSB) to D7 input to the data input terminals D of 0 to FFSB7 are selected as 8-bit digital signals (b0 to b7).

Digital input signals (D0 to D8)
When 1 bit D8 (MSB) is "0", the ground voltage (digital signal "0") input to the data input terminal DT of the flip-flops with switches FFSB0 to FFSB7 is an 8-bit digital signal (b0). ~ B
7) is selected. The selected 8-bit digital signal (b0 to b7) is input to the resistance ladder circuit 12 in synchronization with the synchronization clock CLK input to the clock terminal CK.

In the first embodiment configured as described above, the digital input signal D8 (MS
When B) is "0", all the 8-bit digital signals b0 to b7 to the resistance ladder circuit 12 are "0", and the reference point B of the resistance ladder circuit 12 is the potential of "0". Equivalently, "0" is applied to the output end via the resistance element 2R, which is equivalent to D8 (MSB) being "0" in the conventional D / A converter device of FIG.

Further, in FIG. 1, when D8 (MSB) of the digital input signal is " 1 ", the 8-bit digital signals a0 to a7 to the resistance ladder circuit 11 are all "1", and the resistance ladder circuit 11 is the reference. Since the potential at the point A is "0", "1- (2 to the N-1 power) / 2" is equivalently applied to the output end through the resistance element 2R, as shown in FIG. In the conventional D / A converter device of D8
(MSB) is “1” means that the analog signal output is 1
LSB is reduced and the number of possible values is 2 N-1.
However, in terms of function, the first embodiment operates in the same manner as the conventional D / A converter device of FIG.

Further, since both the reference points A and B are fixed to the potential of "0", the input digital signal (D0) caused by the change of the reference point B occurring in the conventional D / A converter device shown in FIG. The change in the analog signal output of the resistance ladder circuit with respect to the change in D8) does not occur irregularly.

Therefore, the first embodiment operates in the same manner as the conventional D / A converter device of FIG.

However, in the case of the conventional D / A converter device of FIG. 3, the 9-bit digital signal (D8 to D0) changes from "(MSB) 011111111 (LSB)" to "(MSB) 100000000 (LSB)". In this case, the polarity of the resistance element to which the 8-bit digital signal (D7 to D0) signal is applied changes from "1" to "0",
Further, since the polarities of the resistive elements to which the digital signal (D8) signal is applied are all inverted from "0" to "1", the relative accuracy of these resistive elements, especially the digital signal D
The relative accuracy between the resistance element to which the signal of 8 is applied and the other resistance elements greatly affects the analog output voltage, that is, the differential linearity of the D / A converter device. In some cases, there is a problem that the analog output that originally increases due to this change decreases.

On the other hand, the D / A of the first embodiment
In the case of converter device, digital signal (D8-D0)
Also changes from “(MSB) 011111111 (LSB)” to “(MSB) 100000000 (LSB)”, the phenomenon that all the applied polarities to the respective resistance elements are not inverted does not occur, and the differential linearity is broken. There is no such thing.

The difference in operation from the conventional example of FIG. 3 is shown in FIG.
Embodiment) and FIG. 8 (conventional example). In FIGS. 6 and 8, in the state 1, the 9-bit digital signal (D8 to D0) is “(MSB) 0111111111.
(LSB) ", the status 2 indicates that the 9-bit digital signal (D8 to D0) is" (MSB) 1000000 ".
00 (LSB) ”. As can be seen from FIG. 6, in the D / A converter device of the first embodiment,
The applied polarity of each resistance element forming the resistance ladder circuit does not change at all. Therefore, although the analog output does not change at all, it cannot decrease in principle.

In the configuration shown in FIG. 1, for example, the 9-bit digital signal (D8 to D0) is (011111).
When changing from (111) to (100000000), the 8-bit digital signals (a7 to a0) have not changed at all, and the analog signal obtained by converting (011111111) and the analog signal obtained by converting (100000000) Since and have the same value, even if the number of 9-bit digital signals (D8 to D0) increases, the analog signal remains unchanged.

The most problematic aspect of the D / A converter device is that the analog signal output decreases even though the digital input signal increases. In the first embodiment, there is a state in which the analog signal output does not change at all even if the digital input signal increases, but at least it has the effect of preventing the analog signal output from decreasing.

As described above, according to the D / A converter device of this embodiment, the decoder 100 converts a 9-bit digital signal into two 8-bit digital signals, and the two identical configurations are obtained. The 8-bit D / A converter unit has the two 8-bit digital signals respectively converted into analog signals, and the analog signal outputs of the two 8-bit D / A converter units are connected in parallel via resistors R and combined. Then, since it is output as an analog signal of M + N bit resolution, D / A conversion can be realized with a simple repetitive configuration of the resistance ladder circuits 11 and 12 having the same configuration, and good differential linearity can be achieved.

Further, since the 8-bit D / A converter units 11 and 12 are of the R2R voltage addition type composed of the resistance ladder circuit, the area occupied on the chip can be made relatively small.

[Second Embodiment] FIG. 2 shows a second embodiment of the present invention.
2 is a circuit diagram of the D / A converter device of the embodiment of FIG.
In this D / A converter device, the configuration of the decoder 101 is different from that of the first embodiment, and the resistance ladder circuit 1
Other configurations such as 1 and 12 are the same as those in the first embodiment.

The decoder 101 is configured to perform the following operations. That is, the 9-bit digital signal (D8 to D0) is "(MSB) 01111111.
1 (LSB) ", the 8-bit digital signal (a7 to a0) applied to the resistance ladder circuit 11 is" (MS
B) 11111111 (LSB) ", which is an 8-bit digital signal (b7-) to be applied to the resistance ladder circuit 12.
b0) is “(MSB) 00000000 (LSB)”.

A 9-bit digital signal (D8 ...
D0) is "(MSB) 011111111 (LSB)"
When the value is smaller, the 8-bit digital signal (a7 to a0) applied to the resistance ladder circuit 11 is the same value as the 8-bit digital signal (D7 to D0).
The 8-bit digital signal (b7 to b0) applied to the resistance ladder circuit 12 is "(MSB) 00000000 (L
SB) ".

A 9-bit digital signal (D8 ...
D0) is “(MSB) 100000000 (LSB)”
At this time, the 8-bit digital signal (a7 to a0) applied to the resistance ladder circuit 11 is "(MSB) 111111.
11 (LSB) ", and the 8-bit digital signal (b7 to b0) applied to the resistance ladder circuit 12 is" (MS
B) 00000001 (LSB) ".

A 9-bit digital signal (D8 ...
D0) is “(MSB) 100000000 (LSB)”
When it is larger, an 8-bit digital signal (b7-
b0) is always an 8-bit digital signal (D7 ...
It takes a value larger than D0) by "1". However, the 9-bit digital signal (D8 to D0) is "(M
SB) 111111111 (LSB) ", the same value as the 8-bit digital signal (D7 to D0) is output.

In order to execute the above operation, in the decoder 101, for example, an adder as shown in FIG. 10 is added to the input portion of the 8-bit digital signal (D7 to D0) in the decoder 100 of FIG. It is a thing. Specifically, the 8-bit digital signal (D7'-D0 ') output from the adder which receives the 9-bit digital signal (D8-D0) as input is 8 of the decoder 100 of FIG.
It is configured to be input as a bit digital signal (D7 to D0). D8 of the decoder 101 in FIG. 2 is
The same as the decoder 100 of FIG. 1 is input.

This adder is an exclusive OR circuit XOR.
1 to XOR8 and AND circuits AND1 to AND15.

When the D8 is "0", this adder is (D
"0" is added to 7 to D0, that is, (D7 to D0) is output as it is, and when D8 is " 1 ", a value larger by "1" is output to (D7 to D0). But (D7-D
If "0" is all "1" and "1" is added (D7-
Since all of (D0) becomes "0", the product of the inversion of the logical product of (D7 to D0) and D8 is configured as a countermeasure, and even if all of (D7 to D0) is "1", D8 Is "1", "0" is added, that is, (D7 to D0) is output as it is.

By operating in this way, "(MSB)
011111111 (LSB) "to" (MSB) 10
When the analog signal changes to “0000000 (LSB)”, the voltage of the digital signal increases by one code, and although the digital signal changes as in the first embodiment, the analog signal changes. The state in which the signal does not change can be eliminated, and the conversion accuracy can be further improved.

FIG. 7 schematically shows the operation of the D / A converter device according to the second embodiment. 6 and 8 described above
Similarly, state 1 is a 9-bit digital signal (D8 to D
0) indicates the state of “(MSB) 011111111 (LSB)”, and the state 2 indicates a 9-bit digital signal (D8
~ D0) is “(MSB) 100000000 (LS
B) ”is shown. As can be seen from FIG. 7, in the D / A converter device of the second embodiment, the phenomenon in which the applied polarities of the resistance elements forming the resistance ladder circuits 11 and 12 are reversed is None, the differential linearity does not break down.

[Third Embodiment] FIG. 9 shows that a decoder 102 converts a 9-bit digital signal (D0 to D8) into four 7-bit digital signals (a0 to a6, b0 to b).
6, c0 to c6, d0 to d6), and converted into analog signals by the four 7-bit resistance ladder circuits 21 to 24, and the analog outputs of the two resistance ladder circuits are respectively passed through the resistance element R. 3 shows a third embodiment of the present invention which constitutes a D / A converter device which obtains an analog signal corresponding to a 9-bit digital signal by further connecting the connected ones via respective resistance elements R. .

The decoder 102 includes flip-flops with switches FFSA0 to FFSA6 and FFSB0 to FFSB.
6, FFSC0 to FFSC6, FFSD0 to FFSD6
And OR circuits OR1 to OR4 and inverter IN2
1, IN22.

Then, the decoder 102 outputs D7 =
When "0" and D8 = "0", a0 to a6 are D0 to D, respectively.
6, and b0 to b6, c0 to c6, and d0 to d6 are all given "0". Therefore, in the conventional D / A converter device of FIG. 3, b0 to b6 are equivalently D7 = "0", c0. ~ C6
And d0 to d6 perform the same operation as if D8 = "0".

When D7 = "1" and D8 = "0", a0-a
6 is all "1", and b0 to b6 are D0 to D, respectively.
6 is given, and "0" is given to all of cO to c6 and d0 to d6. Therefore, in the conventional D / A converter device of FIG. 3, a0 to a6 are equivalently D7 = "1", c0 to c6 and d0. ~ D6
And the same operation as that of D8 = "0".

When D7 = "0" and D8 = " 1 ", a0 to a
6 and b0 to b6 are all given "1", c0 to c6 are given respectively D0 to D6, and d0 to d6 are all given "0", so equivalently the conventional D / A of FIG. In the converter device, d0 to d6 are D7 = "0", a0 to a6 and b0 to b6.
And the same operation as that of D8 = "1".

When D7 = " 1 " and D8 = "1", a0-a
6, b0 to b6, c0 to c6 are all given "1", and d
Since D0 to D6 are given to 0 to d6, respectively, equivalently, in the conventional D / A converter device of FIG.
"1", a0 to a6 and b0 to b6 perform the same operation as if D8 = "1".

However, this embodiment is different from the conventional D / A converter device of FIG. 3 in the same way as the first embodiment, and when the polarity of the upper bit is inverted, the resistance elements constituting the resistance ladder circuit are connected to each other. Since the phenomenon that all the applied polarities are reversed does not occur, the differential linearity does not break. However, while the first embodiment guarantees the prevention of the breakdown of the differential linearity at the time of the polarity inversion of the upper 1 bit (D8),
This embodiment guarantees the prevention of the breakage of the differential linearity at the time of the polarity inversion of the upper 2 bits (D7, D8).

[0069]

According to the onset light according to the present invention, completely analog signal outputs of the N-bit D / A converter unit connected in parallel combined with M + N bits having the same configuration M-th power of two D
Since the A / A converter device is configured, it not only has the effect of realizing good differential linearity that can prevent at least a decrease in the analog output that originally increases,
It has the effect that it can be configured by extremely simple repetition.
Further, since the N-bit D / A converter unit is the R2R voltage addition type configured by the resistance ladder circuit, the area occupied by the chip can be made relatively small.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a D / A converter device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a D / A converter device according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a conventional D / A converter device.

FIG. 4 is a circuit diagram showing a configuration of another conventional D / A converter device.

FIG. 5 is a circuit diagram showing a configuration of still another conventional D / A converter device.

FIG. 6 is a schematic diagram showing the operation of the D / A converter device of the first embodiment.

FIG. 7 is a schematic diagram showing an operation of the D / A converter device of the second embodiment.

FIG. 8 is a schematic diagram showing an operation of the conventional D / A converter device shown in FIG.

FIG. 9 is a circuit diagram showing a configuration of a D / A converter device according to a third embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration of an adder.

[Explanation of symbols]

11, 12 resistance ladder circuit R, 2R resistance element 100 decoder 101 decoder FFSA0 to FFSA7 switch flip-flop circuit FFSB0 to FFSB7 switch flip-flop circuit

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (2)

(57) [Claims] 1. A D / A converter device for converting an input digital signal into an analog signal, wherein a digital signal of (M + N) bits (where M and N are positive integers) is M bits on the MSB side. N-bit digital signal and, all together with the N-bit digital signal is "1" (2 M square -1) all are "0" in accordance with the value of "0", "1" And L of the digital signal
A decoder for converting an N-bit digital signal having the same N-bit “0” or “1” value on the SB side into one, and 2 M M-bit N-bit digital signals output from the decoder. It is converted to an analog signal, M-th power of two, and a N-bit D / a converter unit having a circuit connection and reference point potential source and the same structure of the N-bit D / a converter unit resistance a R2R voltage addition-type composed of a ladder, N bit D having the identical structure of the second M-th power
/ A converter unit analog signal output terminal resistor
One end of each resistor and the other end of the resistor
If there is only one connection, connect directly to the M + N bit.
Output as an analog signal with
In the case of several, a new resistance is added to the multiple connections.
Connect one end of each to the other end of this new resistor
Connect to the unit and directly from this connection or this connection
A D / A converter device, which outputs as an analog signal of M + N bit resolution via . 2. The input digital signal is converted into an analog signal.
A D / A conversion method for converting into a signal of ( M + N) bits (where M and N are positive integers).
The digital signal is the value of M bit "0" or "1" on the MSB side.
N-bit digital signal that is all "0" according to
And an N-bit digital signal that is all "1"
(2 M-1) and L of the digital signal
N bits that are the same as the values of "0" and "1" of N bits on the SB side
Decoder means for converting the digital signal into one, and 2 M-th power of N bits of the output of the decoder means
Converts each of the digital signals into analog signals
The M-th power source has the same circuit connection and the same potential source at the reference point.
And N-bit D / A converter unit means having
The N-bit D / A converter unit means is a resistor ladder.
Is an R2R voltage addition type conversion means composed of a circuit.
The 2 M power N-bit D having exactly the same configuration
A / A converter unit has one end of a resistor individually connected to the analog signal output terminal, and the other end of the resistor is connected in units of two, and in the case of one connection, an analog signal of M + N bit resolution is directly obtained. and outputs as the connecting portion is double
In the case of several resistors, one end of a new resistor is individually connected to the plurality of connecting portions, and the other end of the new resistor is connected in units of two, either directly from this connecting portion or this connecting portion. A D / A conversion method, characterized in that the analog signal is output as an analog signal of M + N bit resolution via the.