JPS58103214A - Gain controller - Google Patents

Abstract

PURPOSE:To obtain a gain control circuit having a reduced degree of distortion, by combining n and p channel MOS transistors. CONSTITUTION:The p channel MOS transistors (TR) 215a and 216a are distributed in parallel to n channel MOS TRs 215 and 216 which form a signal adding circuit 221a. Therefore the signal produced at a signal output terminal 203 is equal to the synthetic signal obtained by adding the signal produced at the source electrodes of two source follower circuits consisting of MOS TRs 213 and 214 to the signal added through the TRs 215 and 216 and the signal added through the TRs 215a and 216a. Then the same and adverse polarities to the control signal of a control signal input terminal 202 are applied to the gate electrodes of the TRs 215 and 215a respectively. So is with the TRs 216 and 216a of the other side. In such a way, a gain control circuit having a reduced degree of distortion is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gain control device 1 that varies a gain according to a control voltage, and a gain control device suitable for application to a ghost suppression device of a K television receiver. It is related to.

As a prior art most suitable for applying the gain control device of the present invention, the case where it is applied to a ghost removal device of a television receiver will be described below, but the present invention is not limited to this, and other It can also be applied as a gain control circuit.

In recent years, in order to reduce ghost interference in television broadcasts, televisions equipped with ghost removal devices using so-called transversal filters that waveform-equalize video signals have been announced (Proceedings of the 1979 National Television Society of Japan Conference, p.
349 etc.).

FIG. 1 is a block diagram of the television receiver with the ghost removal device. 1 is antenna, 2 is tuner, 3
is an IF'tl1 width circuit, 4 is an upper circuit detection circuit, 5 is a ghost removal device, 6 is a bandpass filter, 7 is a bandpass amplifier circuit,
8 is a color synchronization circuit, 9 is a color demodulation circuit, IO is a video amplifier circuit, 100 is a matrix circuit, and 200 is a cathode ray tube.

The turpentine signal received by the tuner 2 is converted into a video signal by the IF amplifier circuit 3 and the video detection circuit 4, and is input to the ghost removal device 5. The ghost removal device 5 outputs a video signal from which mixed ghost interference components have been removed, as will be described later with reference to FIG.

A carrier color signal is separated from the output video signal of the ghost removal device 5 by a bandpass filter 6, a color difference signal is reproduced by a bandpass amplifier circuit 7, a color synchronization circuit 83 and a color demodulation circuit 9, and a color difference signal is reproduced by a matrix circuit 100. It is combined with the output luminance signal and displayed on the cathode ray tube 200.

FIG. 2 is a block diagram illustrating a ghost removal device 5 according to the prior art. 111 is a video signal input terminal, 11
2 is a video signal output terminal, 11 to 16 are delay elements each having a delay time τ, 21 to 26 are gain control circuits, 101 is a control voltage generation circuit, 102 is a reference signal generation circuit, 103
1 is a comparison circuit, 104 is an addition circuit, and 105 is a subtraction circuit. Further, 401 is a transversal filter consisting of the delay element, a gain control circuit, and an adder circuit.

In the following, the principle of operation of FIG. 2 will be explained.

In the 1 m2 diagram, a video signal subjected to ghost interference is input to a video signal input terminal 111. The transversal filter 401 subjects the video signals taken out from the respective output terminals of the slow te 111 to te 16 to amplitude control in accordance with the control voltage of the control voltage generation circuit 1010 in the gain control circuits 21 to 26, respectively, and then sends the video signals to the addition circuit 104. and add these.

A comparison circuit 103 detects a ghost component from the output signal of the reference signal generation circuit 102 and the video signal from the input terminal 111 that has been subjected to ghost interference. Control voltage generation circuit 1
01 receives the ghost component, and based on this, generates a control voltage so that the output of the transversal filter 401, that is, the output signal of the adder circuit 104, is as equal to the ghost component as possible, and performs the transversal The frequency characteristics of filter 401 are controlled.

Therefore, by subtracting the output signal of the addition circuit 104 and the video signal of the video signal input terminal 111 in the subtraction circuit 105, a video signal from which ghost interference has been removed is obtained at the video signal output terminal 112.

That is, video signal input terminal 1 at a certain time t0
If the video signal of 11 is X, the direct wave signal is V, and the ghost signal is go, then zO= vO+ g.

becomes. Therefore, the video signal y0 generated at the video signal output terminal 112 has the number of delay elements equal to J+a! and each gain of the gain control circuit equal to J+a! t...&1, also the output of the second delay element! 6-P, it can be expressed as follows.

y6=X6- J ap @X6-1 to=1 =vo+ gOJ alF II zoP? −1 As is clear, each gain k of the gain control circuits 21 to 26 is
If you control le&*+...a, '! o=V
o, and the ghost component can be removed.

FIG. 3 is a block diagram showing another prior art ghost removal device. The difference between FIG. 3 and FIG. 2 is that the adder circuit 104 is removed, and the gain control circuits 21 to 21 are removed.
The input signal No. 26 is the signal of the video input terminal 111,
Moreover, each output signal is connected to adder circuits 1041 to 1045 newly provided between delay elements 11 to 16.

The prior art shown in FIG. 3 is a ghost removal circuit that uses what is called a type 9/sparsal filter for input weighting.

Similar to the circuit of FIG. 2 described above, the circuit of FIG. 3 also includes gain control circuits 21 to 26, as is well known.
By controlling the respective gains a, ~a, it is possible to obtain the video signal y0 from which the ghost signal g0 has been removed at the video signal output terminal 112.

As explained above, a gain control circuit is essential to the ghost removal device. The conventional technology of this gain control circuit will be explained below.

FIG. 4 shows a prior art gain control circuit. In the same figure, parts having the same functions as in Figure IIL3 are designated by the same numbers. Although the ag4 diagram shows the configuration of the gain control circuit 21 in the 1gs diagram, other gain control circuits 22 to 2
Of course, the same applies to 6.

201 is a signal input terminal, 202 is a control signal input terminal, 2
03 is a signal output terminal, 211 is a DC voltage source, 213-2
16 is an N-channel MOS) transistor, 217, 2
18 is a DC current source, 219 and 220 are inverting amplifiers, 2
21 is a signal addition circuit, and 222 is a drive circuit.

The gain control circuit shown in Fig. 4 is composed of a MOS transistor, and is designed so that it can be placed on the same semiconductor substrate when the delay element of the ghost removal device described above is composed of a semiconductor device such as a charge transfer element. It is what was done.

The input signal supplied to the signal input terminal 201 is input to an N-channel MOS transistor 213 that constitutes a source follower, and at the same time is inputted to a MOS transistor 213 that constitutes another source follower via an inverting amplifier 219. 214 is also input.

Each source electrode of the MOS) transistors 213 and 214 is connected to the MOS) transistor 2 that constitutes the signal addition circuit 221.
15 and 216. The control signal input terminal 2 is connected to the gate electrode of the transistor 215 (MOS).
A control signal is applied via 02. On the other hand, a control signal is applied to the gate electrode of the MOS transistor 216 via an inverting amplifier.

In the arrangement described above, the well-known MOS transistors 215 and 216 can be thought of as equivalent resistances determined by the voltages of their respective date electrodes, and can therefore be represented as in FIG.

FIG. 5 explains the operation of FIG. 4, and includes 330,
331 is a variable resistor corresponding to the transistors 213 and 214, respectively; 332 and 333 are voltage sources; and 334 is an output voltage terminal. In the same figure, the resistance is 330°331
Assuming that the resistance values are R330 and R331, respectively, the output-pressure (2) can be expressed as in equation (1).

(1) Here, the voltage source 332 corresponds to the source follower composed of the MOS transistor 213 in FIG. , the voltage source 333 corresponds to a source follower configured with a MOS transistor 214.

Based on the formula 9 (1) mentioned above, R331 and R330 (2)
By changing the resistance value, the output voltage v3 can be increased by +v
It will be clear that the gain can be controlled continuously from 1 to -v1.

Next, as shown in FIG. 4, MOS) transistors 215 and 2
The fact that 16 can be isometrically regarded as a resistance will be explained in detail.

FIG. 6 explains the operation of the N-channel MOS transistor. In the figure, 300 is an AC voltage source;
01 is a DC voltage source, and 302 is an output voltage Vout.

303 is a resistor, 304 is an N-channel MOS transistor, and 305 is a variable DC voltage source.

Further, Figure 1m7 is a diagram showing the drain-source voltage versus drain current characteristic of an N-channel MOS transistor. In the same figure, the horizontal axis drain-source voltage VDS
, and the vertical axis represents the drain current ID. As shown in the figure, curves 312, 313, and 314 respectively change the gate-source voltage VGS to VGSI.
, MOS2, MOS3 K selection/v,
This is the drain-source voltage versus drain current characteristic.

It is well known that in this example, the gate-source voltage is increased in the order of curves 312, 313, and 314.

In the i@6 diagram, when the voltage value of the DC current source 301t-VDS is constant and the voltage VGS of the variable voltage source 305 is changed, the drain current flowing through the MOS transistor 304 is as shown in the jI7 diagram. Song 113
12, 313, 314 and the dotted line @301a.

That is, the larger the gate-source voltage, the larger the drain current d flows. And the drain-source voltage V
MOS) transistor 304 when set to a constant voltage value applied to DS t-s dotted line straight $1301m,
The said direct @301 of each curve 312, 313, 314
It can be regarded as a resistance element expressed by a slope near the intersection with m.

Figure 8 is a diagram showing the gate-source voltage versus equivalent resistance value characteristic of an N-channel MOS transistor, where the horizontal axis shows the gate-source voltage VGS, and the vertical axis shows the equivalent resistance value R. .

Further, in FIG. 8, 305& and 305b are predetermined gate-source voltages, 300a and 300b are signal waveforms of the AC voltage source 300 in FIG. 6, and 302m.

302b represents the output voltage 302 in FIG. 46, respectively.

That is, in FIG. 8, the gate-source voltage is
When set to the voltage values shown by 305m and 305b, the output voltage is 302m according to the characteristic curve 316.
, 302b is obtained.

Therefore, in FIG.
It is easy to understand that the resistance value of the output voltage 302 can be controlled by changing the voltage value of the variable DC voltage source 305 connected to the gate electrode of No. 4.

In the gain control circuit 21 of FIG. 4, control voltages of opposite polarity are applied to the gate electrodes of two MOS transistors 215 and 216 to simultaneously control the equivalent resistances of both MOS transistors.

From the above explanation, it can be seen that according to this circuit configuration, the signal output terminal 2
It is obvious that the amplitude value of the output signal applied to the control signal input terminal 203 changes depending on the control voltage supplied to the control signal input terminal 202.

Problems with the prior art will be described below.

The conventional gain control circuit, as explained in FIG.
This method takes advantage of the fact that when the gate-source voltage VGS of the S transistor is changed, the resistance value R between the drain and source changes equimetrically.

Therefore, the change in resistance value is not linear, and there is a problem that distortion occurs in the output voltage depending on the amplitude value of the input signal.For example, as can be seen from a1813i1, the gate
When the source-to-source voltage VGS is given at a voltage value of 305 breaths, the output voltage 302m becomes a distorted waveform in which the lower part of the sine wave input signal is expanded, while the upper part is compressed.
There was a problem in that the input signal could not be accurately transmitted.

The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to
OS) To provide a gain control circuit with less distortion due to transistors.

In order to achieve the above object, in the present invention, MO
S) The signal addition circuit of the gain control circuit that controls the voltage between the gate and source of the transistor is composed of a parallel circuit of an N-channel MOS transistor and a P-channel MOMOS transistor. By taking advantage of the fact that it occurs in polarity, it is arranged so that waveform distortion is canceled out comprehensively.

FIG. 9 is a block diagram of a gain control circuit explaining one embodiment of the present invention. In FIG. 1149, the same functions as in FIG. 4 are denoted by the same numbers. 221a is a signal addition circuit implementing the present invention; 215a;
, 216a is a P-channel MO8)j/ register. .

The difference between the fs9 diagram and the j1!4 diagram is that, as is clear from a comparison of both diagrams, in addition to the N-channel MO8) run sisters 215 and 216 that constitute the signal adder circuit 221a, the P-channel MO8) run sisters 215a and 216a are These points are added in parallel.

Therefore, in FIG. 9, the signal generated at the signal output terminal 203 is transmitted to the MOS transistors 213 and 214.
The signal generated at the source am of the two source follower circuits consisting of the N-channel MO8) range meta 215
This is a composite signal of the signals added by the P-channel MO8) and 216, and the signal added by the run sisters 215a & 216a.

Control signals of the same polarity and opposite polarity to the control signal input terminal 2020 control signal are applied to the gate electrodes of the N-channel transistor 215 and the P-channel transistor 215a, respectively.

That is, when a relatively high voltage is applied to the gate electrode of the N-channel MO8) Runsistor 215 with respect to the source electrode, the P-channel MO8) Runsistor 215
An inverting amplifier 220 is disposed between both gate electrodes of the gate electrode 5a so that a relatively low voltage is applied to the source electrode.

The other ON channel MO8) run sister 216 and P channel MO8) run sister 216a have a similar arrangement.

The operation of the p-channel MO8) run transistors 215m and 216m will be explained with reference to FIGS. 10 and 11.

FIG. 10 explains the operation of the P-channel MO8) Runsistor, and the same functions as those in FIG. JI6 are indicated by the same numbers. 304p is a P-channel MO8) run transistor.

The difference between Figure 1O and Tsuru Figure 6 is that the DC-pressure source 30
The point is that the polarity of 1 is reversed. FIG. 11 is a diagram showing the drain-source voltage versus drain current characteristics of the P-channel MO8) transistor 304p, and the same parts as in FIG. 7 are indicated by the same numbers.

Fig. 11 differs from Fig. 7 in that the source-drain voltage ``vDS (horizontal axis) and the current and drain current ID (vertical axis) are expressed in opposite polarities to those in Fig. 7. m
This is the case when the gate-source voltages are decreased in the order of 312, 313, and 314.

As can be seen from the above explanation regarding FIG.
12, 313, and 314.

Therefore, a P-channel MO having drain-source voltage versus drain current characteristics as shown in figure s11
8) In the Lancisor 304p, as the gate-source voltage is increased, the equivalent resistance increases. It's 316p. In addition, in the same figure Ich, the same parts as in FIG. 8 are indicated by the same numbers.

In Figure 12, the solder pressure between the gate and source is 305 m.
, when set to the voltage value shown by 305b,
Output voltage 302m, 302 according to song @316p
The fact that b is obtained is the same as in the case of the N8 diagram.

On the other hand, the difference from FIG. 8 is that the gate-source voltage VG
Figure 8 shows that when S is increased, the 1-equivalent resistance value R increases, and the output voltage increases accordingly, and the waveform distortion of the output voltage due to the non-linear change in the equivalent resistance value is shown in Figure 8. On the contrary, for one sine wave input signal, the lower part is compressed and the upper part is expanded.

Therefore, as shown in FIG. 9 which is an embodiment of the present invention, N
By combining the channel MO8) run sisters 215, 216 and the P channel MO8) run sisters 5a, 216m, the waveform distortion that has been a problem in the prior art can be mutually canceled out.

In this case, as mentioned above, the N-channel MO8) run transistors 215, 216 and the P-channel MO8)? The gate-source voltage versus equivalent resistance characteristics of the transistors 215a and 216a are opposite to each other, as shown in FIGS. 8 and 12.

Therefore, as a matter of course, the control voltage applied to the gate electrodes of the N-channel MOS transistors 215 and 216 and the P-channel original transistor 215m.

The control voltage connected to the gate electrode of 216a needs to have opposite characteristics. In the circuit of FIG. 9, the inverting amplifier 22
Needless to say, this is achieved with 0.

Also, N-channel MO8) transistor and P-channel MO
8) It is a relatively easy technique to match the characteristics of transistors, especially in semiconductor integrated circuits.
This is the well-known number 9.

FIG. 13 is a block diagram showing an example in which the present invention is implemented in the ghost removal device shown in FIG. 3 described above.

In FIG. 13, parts having the same functions as those in FIGS. 3 and 9 are indicated by the same numbers. The difference between the embodiment shown in FIG. 13 and the conventional example shown in FIG. 3 is that the gain control circuit Jii shown in FIG.
! 121 to 26 are the drive circuit 222 implementing the present invention and the signal addition circuits 221a-1 to 221a- (the only difference is that i is replaced).

As shown in FIG. 13, in the ghost removal device as shown in FIG.
a is not required as many as the number of gain control circuits, and the adder circuit 221
It is easy to understand that the function of the gain control circuit can be realized by providing only the same number of gain control circuits as a.

As described above, the present invention configures a gain control circuit with low distortion by combining an N-channel MO8) transistor and a P-channel MO8) transistor, and is particularly suitable for semiconductor delay lines such as charge transfer elements. The ghost removal device used has high economic value because it can be constructed on the same substrate.

In addition, N-channel MO8) transistor and P-channel MO
8) It is clear that configuring the transistors on the same substrate can be easily realized using the already well-known CMO8 integrated circuit technology.

In addition, in FIG. 9, the MO constituting the source follower
S) If the DC potentials of the source electrodes of the transistors 213 and 214 are set to match, the above-mentioned gain can be achieved by utilizing the bidirectional characteristic that the drain current of the MOS transistor can flow in both positive and negative polarities. By performing the control operation, it is possible to prevent the DC potential of the signal output terminal 203 from changing due to changes in the gate voltage. By doing so, it becomes easy to design other circuit blocks connected to the signal output terminal 203, so it will be easily understood that it is convenient for a circuit designer.

4. Brief explanation of the drawings Fig. 1 is a block diagram of a television receiver incorporating a ghost removal device, Fig. 2 is a block diagram showing an example of a conventional ghost removal device, and Fig. 3 is a block diagram of a conventional ghost removal device. A block diagram showing another example of a ghost removal device, Fig. 1m4 is a block diagram showing the configuration of a gain control circuit according to the prior art, Fig. 5 is an equivalent circuit diagram of a part of Fig. 4, Fig. 6 is a FiN channel MO8) Diagrams 7 and 8 for explaining the operation of transistors
The figures are a drain-source voltage-drain current characteristic diagram and a gate-source voltage-equivalent resistance value characteristic diagram of an N-channel MO8F9 transistor. Figure 9 is a block diagram showing an embodiment of the present invention. Figure 10. Figures 11 and 1 are diagrams for explaining the operation of the P-channel MO8) transistor.
Figure 2 shows a drain-source voltage-drain current characteristic diagram and a gate-source voltage-equivalent resistance characteristic diagram of a P-channel MOS transistor. Figure 13 shows a configuration example of a ghost removal device implementing the present invention. It is a block diagram.

21-26...gain control circuit, 215, 216...
・N channel MO8) transistor, 215m, 2
16a = 4' channel MO8) transistor, 201.
...Signal input terminal, 202...Control signal input terminal, 2
03...Signal output terminal, 219, 220--Inverting amplifier, 221, 221m...Signal addition circuit, 22
2... Drive circuit agent Michihito Hiraki ♂5111 Yu 6# ♂7# sst Possessed to 305a

Claims (3)

[Claims] (1) A first signal input terminal, a second signal input terminal into which a signal of opposite polarity to the signal input to the first signal input terminal is input, a signal output terminal, and the first signal A first MOS of 9N channels has a source electrode and a drain electrode connected between the input terminal and the signal output terminal.
Transistor and P-channel! 2 MOS? a third MOS transistor of N channel and a fourth MOS transistor of P channel; A gain control device comprising gain control signal generating means for applying a predetermined control voltage to the gate electrode of each of the first to fourth MO transistors. (2) A gain control device according to claim 1, characterized in that the DC potentials of the first signal input terminal and the second signal input terminal are substantially the same. (3) Range of the specific FF #fI In the gain control device described in items 1 and 2, the gain control signal generating means has a first control signal output terminal and a second control signal output terminal that output control signals of opposite polarity to each other. a control signal generation terminal, and the first control signal output terminal is a first MOS) transistor, and a fourth MOS)
A gain control device characterized in that the second control signal output terminal is connected to each gate electrode of the transistor, and at the same time, the second control signal output terminal is connected to the gate electrode of the first MOS transistor and the first MOS transistor.