RU2642538C1 - Integrated attenuator - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: integrated attenuator contains a differential signal generator, links consisting of parallel controlled metal-nitride-oxide-semiconductor transistor of n and p type, a control unit and a load, in addition, a non-inverting pair of links consisting of n-type and p-type metal-nitride-oxide-semiconductor transistor is connected to the differential signal generator and the load directly, and an inverting pair of links consisting of metal-nitride-oxide-semiconductor transistor of n- and p-type is connected to the differential signal generator and the load crosswise; where the resistance of the metal-nitride-oxide-semiconductor transistors entering the links is controlled by the control unit, while the resistance of one pair of metal-nitride-oxide-semiconductor transistor links increases and the other drops.

EFFECT: providing the possibility of expanding the functionality of attenuators made with CMOS technology, reducing losses in direct signal passage, increasing the dynamic range, expanding the bandwidth of operating frequencies, reducing phase distortions when switching attenuation levels.

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Description

Technical field

The invention relates to electronic equipment and can be used in the development of semiconductor CMOS (complementary metal-oxide-semiconductor) circuits for creating differential radio frequency and microwave (microwave) attenuators with a wide frequency band, the required attenuation step, low phase distortion and an increased level of signal linearity.

State of the art

Microwave attenuators made on the basis of semiconductor devices are widely used in microwave technology, especially multi-bit microwave attenuators with discrete attenuation, which are a cascade connection of several discharges, each of which is a P- or T-shaped connection of resistors, which are closed by keys in accordance with with the submitted digital code.

The prior art also knows methods for constructing analog electronic attenuators made by CMOS technology. An analog attenuator is an electronic device that allows you to attenuate the input signal according to a continuous law.

Known analog attenuator, built on the basis of the source repeater circuit [1]. In the circuit, the drains of two p-type MOSFETs are connected to ground, and the sources are connected to a current source. An input signal (Vin) is supplied to the gate of the first transistor, and a constant voltage is applied to the gate of the second transistor, which controls the amount of attenuation (Vbias). The output is removed from the drains of MOS transistors.

The principle of operation of the specified analog attenuator is that a change in the resistance of the second transistor leads to a change in the transfer coefficient of the circuit.

A well-known source [2], which presents a differential version of an analog attenuator based on a source follower. Compared to a unipolar attenuator in differential voltage, the gates of the control transistors are fed through an RC filter. In this case, the control signal from the non-inverting input is supplied to the transistor, which controls the amount of attenuation of the signal from the inverted input. This inclusion allows you to suppress the common mode component of the input signal.

Known attenuators have the following disadvantages: a narrow range of operating frequencies, a narrow dynamic range, complexity of construction and large losses of multi-bit attenuators due to the use of a fixed control voltage.

Disclosure of invention

The technical result to which the claimed invention is directed is to expand the functionality of attenuators made according to CMOS technology, reduce losses during direct signal passage, increase the dynamic range, expand the operating frequency band, decrease phase distortion when switching the attenuation level.

The specified technical result is achieved by the fact that the claimed integral attenuator contains a differential signal generator, links consisting of parallel connected MOSFETs of n- and p-type, a control unit and a load, in addition, a non-inverting pair of links consisting of MOSFETs of n- and p-type is connected to the differential signal generator and the load directly, and an inverting pair of links consisting of MOSFETs of n- and p-type is connected to the differential signal generator and the load godmother; where the resistance of the MOS transistors included in the links is adjusted by the control unit, while the resistance of one pair of MOS transistor links increases and the other falls.

When constructing the switch, differential bridge building circuits are used, which allow, firstly, to reduce the influence of stray inductances connected to the common bus and, secondly, using the compensation effect (signal reduction due to addition to the signal of opposite polarity), to ensure signal attenuation without the use of cascading attenuators with a fixed amount of attenuation. To increase the dynamic range, parallel connection of MOS transistors of n- and p-types is used. Digital control of the proposed attenuator can be provided by a control unit that converts digital codes to the required values of the bias voltages of the transistors.

Brief Description of the Drawings

The essence of the utility model is illustrated by the drawing, where in FIG. 1 shows a block diagram of an attenuator made on MOS structures, where:

1 - differential signal generator;

2, 3, 4, 5 - links consisting of a parallel connection of MOSFETs of n- and p-type;

6 - load;

7 - control unit.

The control unit converts the external control signals to the required offset levels. The parallel connection of n- and p-type transistors at each MOS link provides better signal transmission linearity compared to using the same type of transistors. When the resistance of the through links 2 and 5 is equal to the resistance of the compensating links 3 and 4, the signal is attenuated to the maximum. With the maximum opening of the transistors of the through links, i.e. the minimum resistance of the connecting links and the corresponding increase in the resistance of the compensating links provides direct signal passage with minimal losses. With the correct choice of complex impedances of links, when the impedance of links 2 and 5 increases in proportion to the decrease in impedance of links 3 and 4, matching with the signal source is ensured over the entire range of adjustment of the transmission coefficient.

In addition to supplying continuous values to the control terminals, the resistance value of MOS transistors can also be controlled digitally, while transistors with an n-type channel are controlled by signals from the digital control unit: an1, an2, bn1, bn2, and MOS transistors are p-type signals: ap1 , ap2, bp1, bp2, respectively.

The implementation of the invention

The operation of the device is as follows.

In the block diagram of FIG. 1, the signal from the differential signal generator 1 is supplied to links 2-5, which are controlled from the control unit 7 so that when the MOS transistors in links 2 and 5 of the MOS are opened, the transistors in links 3 and 4 are closed. With the same resistance of all links, the signal at load 6 will be minimal, and vice versa, with a minimum resistance of links 2 and 5 and a maximum resistance of links 3 and 4, the signal loss at the output will be minimal. Thus, by changing the potential at their gates inside the resistance links of MOS transistors, it is possible to control the output signal with the required step. Provided that the product of the resistances of the links with decreasing and increasing resistances is equal, it is possible to match the signal with the source and load 6. Regulation is carried out by the control unit 7, which can be controlled by either an analog signal or a digital one (when using digital-to-analog in the control unit 7 Converter - DAC), providing smooth (analog) or discrete (digital) adjustment of signal attenuation.

In FIG. Figure 2 shows, as an example, a family of curves showing the signal variation by the attenuator for various DAC codes over a wide frequency range.

The results obtained using the CMOS technological process with a minimum size of 0.25 μm are shown in Table 1.

The values of these parameters are much better than previously obtained for comparable CMOS technological processes.

The integral attenuator is implemented as a monolithic CMOS integrated circuit on a single chip.

Information sources

1. T.N. Theo, Low-Power Digitally Controlled CMOS Source Follower Variable Attenuator, IEEE ISCAS 2007, New Orleans, LA, May 27-30, 2007.

2. Patent for an invention. US No. 0295594. Source Follower Attenuator / T.H. Theo, publ. 10/25/2010.

Claims (1)

An integral attenuator containing a differential signal generator, links consisting of parallel-connected controlled MOSFETs of n- and p-type, a control unit and a load, characterized in that the non-inverting pair of links consisting of MOSFETs of n- and p-type is connected to the generator differential signal and load directly, and an inverting pair of links consisting of MOSFETs of n- and p-type is connected to the differential signal generator and the load crosswise; where the resistance of the MOS transistors included in the links is adjusted by the control unit, while the resistance of one pair of MOS transistor links increases and the other falls.

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