JP3480567B2 - Nonvolatile semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a C / C used in a system for displaying images or characters, such as a television or a computer.
For use in a distortion correction circuit for deflection current of RT, in particular, M
The present invention relates to a function generation circuit suitable for being implemented as an OS type semiconductor integrated circuit device. 2. Description of the Related Art Conventionally, a circuit for correcting distortion of a deflection current of a CTE can be found, for example, in the NHK Television Technical Textbook (above), edited by the Japan Broadcasting Corporation, pages 233 to 234 (1989). In addition, there has been known a circuit method for obtaining a square waveform (parabolic waveform) as a distortion correction waveform using resonance between a deflection coil and a capacitor. [0003] Unlike a television, a CRT display monitor such as a personal computer or a work station may have several types of deflection frequencies prepared. In this case, the conventional circuit system described above uses the deflection frequency. With the change, the amplitude of the distortion correction waveform changes. Further, since the deflection frequency is detected, a switch is switched by the detected output, and a constant such as a capacitor is switched, a large number of individual components are used, which is not suitable for integration into an integrated circuit. On the other hand, the required amplitude of the distortion correction waveform is determined by the shape of the tube surface of the CRT used, and a constant amplitude is required regardless of the change in the deflection frequency. The present invention provides a circuit suitable for integration into a circuit, which generates a distortion correction waveform having a constant amplitude regardless of a change in deflection frequency. [0005] The present invention provides two MOS transistors.
The source electrode of the transistor is commonly connected to the inverting input terminal of the operational amplifier, the output terminal of the operational amplifier and the inverting input terminal are connected by a resistor, and an input signal is applied to the drain of one MOS transistor. In a so-called adder circuit for applying a waveform of the opposite polarity of the input signal to the drain of the MOS transistor, the gate voltage of the two MOS transistors is made similar to the waveform of the input signal, and the source / drain resistance of the MOS transistor is changed in proportion to the input. To obtain a squared waveform of the input waveform. According to the present invention, the amplitude of the squared waveform, that is, the distortion correction waveform is affected only by the amplitude of the input waveform, and does not depend on the frequency. A first embodiment of the present invention will be described with reference to FIGS. In FIG. 1, the drain electrode of the MOS transistor 1 is connected to the positive input terminal, and the source electrode is connected to the inverting input terminal of the operational amplifier 4. The drain electrode of the MOS transistor 2 is connected to the negative input terminal, and the source electrode 4 is commonly connected to the inverting input terminal of the operational amplifier 4. Here, a signal -Vin having a polarity opposite to that of the input signal Vin applied to the positive input terminal is applied to the negative input terminal. The non-inverting input terminal of the operational amplifier 4 is at the reference potential, and the output terminal is MO.
Connected to the source electrode of S transistor 3. MO
The drain electrode of the S transistor 3 is connected to the inverting input terminal of the operational amplifier 4. Since the gate voltage of the MOS transistor 3 is connected to the fixed voltage VG, M
The OS transistor 3 has the same function as a constant resistance. Therefore, the MOS transistor 3 can be replaced with a resistor. Assuming that a waveform similar to the input signal Vin is Va and the ground potential is VG, a voltage of VG−Va is applied to the gate electrode of the MOS transistor 1 and a voltage of VG + Va is applied to the gate electrode of the MOS transistor 2. Is done. Hereinafter, the input / output characteristics of the circuit will be described first. The gates of the MOS transistors 1, 2, and 3
The source-to-source voltages are VGS1, VGS2, and VGS3, the threshold voltage is VTH, and the voltage-current conversion factor of the MOS transistor is K.
And When the drain-source voltage of the MOS transistor is sufficiently small, the resistance R1 of the MOS transistor
In general, R1 = 1 / ｛K ・ (VGS1-VTH)｝, R2 = 1 / ｛K ・ (VGS2-VTH)｝, R3 = 1 / ｛K ・ (VGS3-VTH)｝… ( It is expressed by 1). On the other hand, the input / output characteristics of the circuit shown in FIG. 1 can be represented by Vin / R1−Vin / R2 = −Vout / R3 (2) as generally called an adder. By substituting equation (1) into equation (2), Vin ・ K ｛{(VGS1-VTH)-(VGS2-VTH)} =-K ・ (VGS3-VTH) ・ Vout (3) where VGS1 = VG-Va, VGS2 = VG + Va, VGS3
= VG, substituting 2 · Vin · Va = (VG−VTH) · Vout (4) Where Va is a similar waveform of Vin and its proportional coefficient is α, α · Vin2 = (VG−VTH) Vout (5) That is, a square waveform of the input is obtained at the output. FIG. 2 shows waveforms at various points in the circuit of FIG. Here, Vin rises linearly over time or falls linearly. Va is Vin
Multiplied by the proportional coefficient α, VG + Va is applied between the gate and source of the MOS transistor 2, and VG−Va is applied to the MOS transistor 2.
It is added between the gate and the source of the transistor 1.
The output voltage Vout has a square waveform corresponding to each of a rising section and a falling section of the input Vin. Here, the output amplitude depends only on the input voltage, as is apparent from the equation (5), and has no relation to the frequency or the slope. A second embodiment of the present invention will be described with reference to FIGS. In the circuit of FIG.
The portion composed of the operational amplifiers 2 and 3 and the operational amplifier 4 is the same as the circuit of FIG. The former part has resistors 5, 6, 7, 8, 9, 10,
A voltage dividing circuit composed of 11 and 12 and an operational amplifier 2
7, 28, resistors 13, 14, 15, 16, 17, 18,
It comprises three parts: a single-ended differential conversion circuit composed of 19 and 20, and a signal switching circuit composed of switches 21, 22, 23, 24, 25 and 26. Hereinafter, the circuit operation will be described in order from the input side. The switches 21 to 26 of the signal switching circuit are controlled by switching control signals Sa to Sf, respectively. Sa turns on the switch 21 in the odd-numbered rising section of the input signal. S
c turns on the switch 23 in the odd-numbered falling section and the even-numbered rising section of the input signal. Se turns on the switch 25 in the even-numbered falling section. Remaining Sb and Sd
, Sf operate one cycle behind Sa, Sc, Se.
That is, Sb turns on the switch 22 in the even-numbered rising section of the input signal. Sd turns on the switch 24 in the even-numbered falling section and the odd-numbered rising section of the input signal. Sf turns on the switch 26 in the odd-numbered falling section. Therefore, the output Va of the signal switching circuit is the same as the input signal in the odd-numbered rising section of the input signal, the same voltage as VB in the odd-numbered falling section and the even-numbered rising section, and the even-numbered falling section. Then, the voltage becomes the same as VBN. Similarly, the output Vb of the signal switching circuit is the same as the input signal in the even-numbered rising section of the input signal, the same voltage as VB in the even-numbered falling section and the odd-numbered rising section, and the odd-numbered falling section. In the section, the voltage is the same as VBN. Next, in the single-ended differential conversion circuit, V
a and Vb are subtracted. Generally, assuming that the outputs are Vc and Vd and the resistances 13 to 20 are all equal, Vc = (Vb−Va) and Vd = −
(Vb-Va). Vc and Vd are V
It becomes a signal whose polarity is inverted with respect to b. In the next voltage divider, the output of the single-ended differential converter is divided. The reason for the voltage division is that the linear operation range of the MOS transistors 1 and 2 is narrow. At the same time, in this voltage dividing circuit, the gate voltages of the MOS transistors 1 and 2 are generated. As described above, the gate voltage needs to be a signal similar to the input signal centered on the potential of VG. The drain voltage Vin of the MOS transistor 1
+ And the drain voltage Vin- of the MOS transistor 2 are obtained by changing the resistance values of the resistors 7, 8, 11 and 12 to R7, R8 and R1 respectively.
1, R12: Vin + = Vc R8 / (R7 + R8) (6) Vin- = Vd R12 / (R11 + R12) (7) The gate voltage Vf of the MOS transistor 1 and the gate voltage Ve of the MOS transistor 2 are resistors. Assuming that the resistance values of 5, 6, 9 and 10 are R5, R6, R9 and R10, respectively, Ve = Vdd · R6 / (R5 + R6) + VC · R5 / (R5 + R6) (8) Vf = Vdd · R10 / (R9 + R10) + Vd.R9 / (R9 + R10) (9) Assuming that R5 = R9 and R6 = R10, Ve and Vf are constant voltages Vdd.R6 /, as can be seen from equations (8) and (9).
Signals obtained by dividing Vc and Vd around (R5 + R6) = VG are output. In equation (5), α is given by the following equation (6) for the input signal:
Considering that the pressure is divided by the equation (7), R7 = R
11, when R8 = R12 α = R99R12 / (R9 + R10) ・ (R11 + R12) (10) (5) Vin in the equation (5) is only for the rising section of the input Vin R8 / (R7 + R8) = Vin + Vin -... (11), and the square waveform of the input is obtained at the output from the equation (5). Vc, Vd, Ve, V
Since f is clamped to the peak value by the switches 21 to 26, the output value is also clamped to the peak value. As described above, the circuit shown in FIG. 3 outputs a square waveform only during the rising section of the input, and outputs a constant value during the falling section of the input having a short time, and does not output a square waveform. In a distortion correction waveform generation circuit of a CRT such as a television, a falling section is a section called a retrace section in which an image is not visible on a screen. When a waveform is output, it is necessary to amplify the frequency characteristics of the amplifier circuit connected to the subsequent stage to a relatively high frequency so that the influence does not affect the squared waveform in the rising section. If the circuit shown in FIG. 3 is applied to a distortion correction waveform generating circuit of a CRT, the frequency characteristics of an amplifier circuit connected at the subsequent stage may amplify a relatively low frequency. As described above, according to the present invention, M
Using the OS transistor, a CRT distortion correction waveform generation circuit can be realized. Furthermore, since the switch can be easily realized and changed with a MOS transistor, when applied to a MOS type integrated circuit, a distortion correction waveform generation circuit of a CRT can be configured without adding a function of switching a capacitor externally. There is. Further, since the output in the retrace interval can be clamped to a constant value and unnecessary high-frequency waveforms are not output, there is an effect that the frequency characteristics of the circuit connected to the subsequent stage can be reduced.

[Brief description of the drawings] FIG. 1 shows a first embodiment of the present invention. FIG. 2 shows operation waveforms of various parts of the circuit of FIG. FIG. 3 shows a second embodiment of the present invention. FIG. 4 shows operation waveforms of various parts of the circuit of FIG. [Explanation of symbols] 1,2,3 MOS transistor 4 Operational amplifier 5-20 resistor 21-26 switch

Claims (1)

(57) a first input terminal for inputting the Patent Claims 1. A sawtooth signal, a second input terminal for receiving a first reference voltage, a third for inputting the second reference voltage An input terminal, a fourth input terminal for inputting a third reference voltage, and first, second, third, fourth, and fourth signals for sequentially switching signals input to the input terminal group.
Fifth and sixth switches, first and second differential amplifiers for inputting signals selected by the switches, and first and second differential amplifiers for inputting the first and second differential amplifiers, respectively. A first MOS transistor having first, second, third, and fourth output terminals attached to two voltage dividers comprising a second resistor group, and a drain connected to the second output terminal; A second MOS transistor having a drain connected to the output terminal of the second MOS transistor, a source of the first MOS transistor and a source of the second MOS transistor connected in common, and an inverting input terminal connected thereto; An operational amplifier connected to a non-inverting input terminal, and a resistance element having a first terminal connected to the inverting input terminal and a second terminal connected to an output terminal of the operational amplifier; Transistor gate The third is connected to the output terminal, the function generator having a gate and being connected to said first output terminal of said second MOS transistor.