USRE28579E

USRE28579E - Integrating network using at least one D-C amplifier

Info

Publication number: USRE28579E
Authority: US
Priority date: 1969-06-03
Filing date: 1974-05-30
Publication date: 1975-10-21

Abstract

An integrating network for performing integration of an input voltage by the use of an integrator comprising time-constant means and a d-c amplifier, wherein a drift memory circuit is provided between the output and input of the integrator for feeding back from (in the opposite polarity) from the output of the d-c amplifier to (the) an input terminal of the integrator, a feedback signal of polarity in opposition to the input voltage in a case of no input of the d-c amplifier so as to obtain a stationary condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the stationary condition, the feedback signal having a value substantially equal to the drift voltage of the dc amplifier converted in terms of the input of the d-c amplifier, whereby an input voltage is integrated in the integrating network without error caused by the drift of the d-c amplifier.

Description

United States Patent 1191 Uchida [11] E Re. 28,579

[ 1 Reissued Oct. 21, 1975 1 1 INTEGRATING NETWORK USING AT LEAST ONE D-C AMPLIFIER [75] Inventor: K010 Uchida, Tokyo, Japan [21] Appl. No.: 474,806

Related U.S. Patent Documents [58] Field of Search 307/297, 229, 238; 328/127, 328/128; 330/9; 235/183 56] References Cited UNITED STATES PATENTS 3,070,786 12/1962 Maclntyre 307/297 3,072,856 l/1963 Close 328/127 3,147,446 9/1964 Wittenberg 330/9 Va :4 R 2 10 3,167,718 1/1965 Davis et al 307/229 3,246,171 4/1966 White r 307/229 3,382,461 5/1968 Wolcott 330/9 3,541,320 11/1970 Beall 330/9 OTHER PUBLICATIONS Automatic Drift Compensation in DC. Amplifier, by Cederbaum, et. al., pp. 745-747, Rev. of Sci. Inst., August, 1955, Vol. 26, No. 8.

Primary Examiner-Michael J. Lynch Assistant Examiner-B. P. Davis Attorney, Agent, or FirmRobert E. Burns; Emmanuel J. Lobato; Bruce L. Adams [57] ABSTRACT An integrating network for performing integration of an input voltage by the use of an integrator comprising time-constant means and a d-c amplifier, wherein a drift memory circuit is provided between the output and input of the integrator for feeding back [in the opposite polarity] from the output of the d-c amplifier to [the] an input terminal of the integrator, a feedback signal of polarity in opposition to the input voltage in a case of no input of the d-c amplifier so as to obtain a stationary condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the stationary condition, the feedback signal having a value substantially equal to the drift voltage of the d-c amplifier converted in terms of the input of the d-c amplifier, whereby an input voltage is integrated in the integrating network without error caused by the drift of the d-c amplifier.

21 Claims, 16 Drawing Figures Reissued Oct. 21, 1975 Sheet 1 of9 Re. 28,579

Reissued 0a. 21, 1975 Sheet 2 of9 Re. 28,579

Reissued Oct. 21, 1975 Sheet 3 of9 Re. 28,579

Reissued Oct. 21, 1975 Sheet 5 of9 Re. 28,579

25 f Y 27 PULSE GENERATOR COUNTER a 23 J a 1 s A 1 2 I i LEVEL i i DETECTOR I Reissued 0m. 21, 1975 Sheet 6 0f 9 Re. 28,579

Q LI

fob

Fig. 12

Reissued Oct.2l, 1975 Sheet? of9 Re. 28,579

25 2a" 27 P U L 5 E A C OUN TE R GENERATOR 4a f F MULTI- 5 V/BRATOR 5 SWITCH CONTROL CIRCUIT Reissued Oct. 21, 1975 Sheet 8 of9 Re. 28,579

Fig. 15

Reissued Oct. 21, 1975 Sheet 9 of9 Re. 28,579

COUNTER PULSE GENERATOR I I I l l l I I P 1 0 I ll.

VIBRA TOR SWITCH CONTROL CIRCUIT Fig. 16

INTEGRATING NETWORK USING AT LEAST ONE D-C AMPLIFIER Matter enclosed in heavy brackets 1 appears in the original patent but forms no part of this reissue specification; matter printed in italics indicates the additions made by reissue.

This invention relates to integrating networks having an output waveform corresponding to the time integral ofits input waveform and more particularly to integrating [network] networks using at least one directcurrent amplifier.

In conventional integrating networks for obtaining an integrated value corresponding to the time integral of the input signal, a d-c amplifier is usually used. In this case, stability and no-drift are required of the d-c amplifier since an integrating error is caused by the drift. To reduce the value of the drift, chopper amplifiers are frequently used. However, the drift is still appreciable in the chopper amplifier, so that the value of drift is a main factor for determining the preciseness of integration. The above-mentioned drift can be eliminated by drift-compensation which is manually carried out for zero adjustment. However, it is very troublesome to perform such manual adjustment at every integration. Moreover, it is very difficult to always obtain correct results by [the] manual adjustment.

An object of this invention is to provide integrating networks capable of eliminating the above-mentioned defects of the conventional art and capable of readily performing zero adjustment with certainty.

Another object of this invention is to provide integrating networks suitable for highly reliable analoguedigital converters.

In accordance with the feature of this invention, there is proposed an integrating network for performing integration of an input voltage by the use of an integrator comprising time-constant means and a d-c amplifier, characterized in that a drift memory circuit is provided between the output and input of the integrator for feeding back [in the opposite polarity from the output of the d-c amplifier to [the] an input ter minal of the integrator, in a case of no input of the d-c amplifier, afeedback signal of polarity in opposition to the input voltage so as to obtain a stationary condition, and for continuously sending out, as afeedback signal. a voltage fed back to the input of the integrator at the stationary condition, the feedback signal having a value substantially equal to the drift voltage of the d-c amplifier, whereby an input voltage is inte grated in the integrating network without error caused by the drift of the d-c amplifier.

The principle, construction, operation and merits of this invention will be better understood from the following more detailed discussion in conjunction with the accompanying drawings, in which similar parts are designated by the similar reference numerals, characters and symbols, and in which:

FIG. I is a waveform diagram explanatory of drift in a d-c amplifier used in this invention;

FIG. 2 is a block diagram illustrating an embodiment of this invention;

FIG. 3 is a block diagram illustrating a modification of the embodiment shown in FIG. 2;

FIGS. 4, 5, 6 and 7 are block diagrams each illustrat ing an embodiment of this invention;

FIG. 8 is a waveform diagram explanatory of the effect of drift in a dc amplifier used in an analoguedigital converter using an integrating network of this invention;

FIGS. 9, l1 and 14 are block diagrams each illustrating an example of the invention suitable to form an analogue-digital converter;

FIGS. l0, l3 and 16 are block diagrams each illustrating an analogue-digital converter using an integrating network of this invention;

FIGS. 12 and 15 are time charts explanatory of operations of the examples shown in FIGS. II and 14.

With reference to FIG. I, the concept of how an integration error is caused by the drift in a d-c amplifier used in an integrator is at first described. If it is assumed that the voltage of an input signal and the time constant of an integrator are values V, and RC respectively, an output waveform V having the gradient (V /RC) is obtained at the output of the integrator in response to the voltage V; of the input signal applied if the d-c amplifier employed in the integrator has no drift. In this case, the output waveform V would reach a voltage V,,, equal to a value (V,.t/RC) at a time T delayed by a time t after a time T, when the output waveform V exceeds a predetermined reference level (e.g.; zero level Lo).

However, if the d-c amplifier drifts, the output waveform V would reach a value (Vd.t,/RC) at the time T even if the voltage V, of the input signal is zero; where the value Vd is a value of drift converted in terms of the input of the integrator. Accordingly, if the input voltage V. of the input signal is applied to the integrator having the drift Vd, the output waveform V has the gradient (Vi Vd)/RC and reaches a value Voa =(V, Vd)t /RC at the time T, delayed by the time t, after the time T,, when the output waveform V exceeds the zero level Lo. In other words, an error [(Voa- Vo)l](V0a- Vol) equal to a valueVd.t /RC is a result of the drift Vd.

As mentioned above, drift is a main factor of error in the conventional integrating network. To reduce the error to a minimum, an amplifier (e.g.; chopper amplifier) having only a small drift has been employed, However even with such a provision, the elimination of errors is not sufficient while the cost of the integrating network is relatively high.

In accordance with the principle of this invention, a compensating voltage Vd is continuously applied to the input of the integrator in addition to the input voltage Vi of the input signal before every integration if the value of drift converted in terms of the input of the integrator is a value Vd. As a result of this feature of this invention, the drift can be effectively eliminated without use of an expensive chopper amplifier to provide a reliable integrator of low cost.

With reference to FIG. 2, an embodiment of this invention comprises

input terminals

1 and 2 for applying an input signal to be integrated, a switch 3 connected between a common terminal 7 and one of two

terminals

4 and 5, an integrating register 8, an integrating capacitor 9, a d-c amplifier 11 having a sufficient gain and producing an output whose polarity is reverse to the polarity of the input signal applied to the input 10 of the amplifier 11, an output terminal 12, a switch 13, a capacitor 14, a field-effect transistor I6 having a gate IS, a resistor 17 applying a necessary voltage between the drain and source of the field effect transistor 16 from d-c power terminals +8 and B, and a connection line 18 connecting the source of the field-effect transistor 16 to the terminal 4 of the switch 3. The integrating resistor 8, the integrating capacitor 9 and the d-c amplifier 11 form an integrator. The capacitor 14, the field effect transistor 16 and the resistor 17 forms a drift memory circuit as understood from the following description.

In this embodiment shown in FIG. 2, if it is assumed that a value of drift converted in terms of the input of the integrator is a value Vd, this converted drift is equivalently applied across the common terminal 7 and the ground potential. In this case, if the common terminal 7 of the switch 3 is connected to the terminal 4 so as to make the input signal V,- zero at the common terminal 7, a current Vd/R flows through the resistor 8 having a resistance R so that the capacitor 9 (having a capacitance C) is charged. The output wave form V obtained at the output terminal I2 is a linear wave form having the gradient Vd/RC'. Therefore, when this in tegrating network attains a stationary condition after connection between the

terminals

4 and 7 and switchin of the switch 13, respective potentials of the input 10 of the amplifier 11 and the connection line 18 are equal to each other so that no current flows in the resistor 8. In this case, the potential to ground of the connection I4 is a voltage which causes the potential Vd to the ground of the connection line 18.

In this connection, after the switch 13 is switched-off and the

terminals

5 and 7 are connected to each other, the input signal V, is applied across the terminals I and 2. Since the potential to ground of the input terminal 2 is a value -Vd due to the charged voltage of the capacitor 14, a current i which is obtained by dividing, by the resistance R of the resister 8, the sum of the potential to ground -Vd of the terminal 2, the value of drift Vd converted in terms of the input terminal and the input signal Vi flows through the resister 8. Namely:

Accordingly, a linear waveform having the gradient Vi/RC is obtained at the output terminal 12 as an output voltage Vo. At a time T, delayed by a time t, from a time T, when the output voltage V0 exceeds the zero level Lo, the output voltage Vo reaches a value -Vi.t /RC.

As mentioned above, a highly reliable integrator can be provided by detecting the drift Vd converted in terms of the input terminal before the performance of integration and by compensating the drift of the integrator by the use of the detected drift value.

lfa chopper amplifier etc. having a limited small drift is employed as the d-c amplifier 11, the preciseness of integration of the integrator raises further. The

switches

3 and 13 may be formed by a desired type, such as mechanical switch or electronic switch.

In order to reduce [a] the detecting-and storing time necessary to detect and store the drift value after connection between the

terminals

4 and 7 at the switch 3, namely [a] the time necessary to reach [the] a stationary condition in a loop (

terminals

4 and 7 the resistor 8 the amplifier 11 the switch 13 the field-effect transistor 16), the integrating capacitor 9 may be disconnected from the input or output of the amplifier 1] at the detecting-and-storing time.

In the embodiment shown in FIG. 2, the field-effect transistor [6 is connected as a source follower. However, this source follower may be replaced by an amplifier or an attenuator. Moreover, an amplifier or an attenuator may be inserted between the output of the d-c amplifier 11 and the output terminal 12. These embodiments will be successively described below in detail.

The switch 3 maybe inserted between the integrating resistor 8 and the input 10 of the d-c amplifier 11 as shown in FIG. 3. In this embodiment, operations similar to the embodiment shown in FIG. 2 can be performed.

In these embodiments, if necessary a resistance may be inserted in the connection line 18.

As mentioned above, the sum (Vi e Vd) of the input signal Vi and the output (Vd) of the drift memory circuit is applied during the time t, to the input of the inte grator so that the drift Vd is compensated. Accordingly, if the stability of the integrator and the drift memory circuit is sufficient during the time t,, an error of integration caused by drift which continues also after the time t can be completely eliminated. Moreover, since a d-c amplifier having an extremely small drift is not an essential means, the integrating network of this invention can be formed at low cost.

In the above-mentioned embodiments, if an active circuit is connected at the preceding stage of the integrating network, the apparent voltage of a d-c power source of the preceding active circuit is equivalent to the sum of the voltage (+B) of the d-c power source and the converted drift voltage (Vd) in the feedback signal. Accordingly, a separate d-c power source is necessary.

With reference to FIG. 4, an embodiment of this invention which does not require a separate d-c power source of the preceding stage even if an active network is connected to the preceding state will be described. In this embodiment, a differential amplifier lla having two [inputs]

input terminals

10a and 10b is employed in place of the d-c amplifier 11 having the single input 10 in the embodiments shown in FIGS. 2 and 3. Moreover, a d-c amplifier I9 having a single input is employed in place of the source follower of the embodiments shown in FIGS. 2 and 3. The differential amplifier lla has [a sufficient 1 an amplification factor u and the polarity of the input terminal 10a is reverse to the polarity of the output terminal 12 of the amplifier lla while the I. The polarity of the input terminal 10b is the same as the polarity of the output terminal of the amplifier 11a. The d-c amplifier 19 has an amplification factor u and the polarity of the input terminal of this amplifier I9 is reverse to the polarity of the output terminal thereof. The d-c amplifier 19, a switch 13 and a capacitor 14 form a drift memory circuit 20 which feeds back the output signal of the differen rial amplifier 110 I0 the other input terminal lOh therenfin the same polarity us that ofthe input terminal as mentioned above. A converted drift voltage as mentioned below is applied to the input 10b through a connection line 183 from the drift member circuit 20. The terminal 4 of the switch 3 is grounded, while other parts are the same as the parts of the embodiments shown in FIGS. 2 and 3.

In operation, the common terminal 7 of the switch 3 is connected to the terminal 4 while the switch I3 is switched-on. In this case, ifit is assumed that respective drift voltages of the

amplifiers

11a and 19 converted in terms of the respective inputs are a value V, (at the input terminal a) and a value V the output voltage V of the output terminal I2 is as follows:

mlvgug v l.

Therefore, a voltage V 2 of the input terminal 10b becomes equal to the converted voltage V, so that no current flows in the resistor 8. In this case, a quiescent condition is established.

Thereafter, when the switch 13 is switched-off while the common terminal 7 of the switch 3 is connected to the terminal 5, an input voltage applied across the terminal I and the ground is integrated by an integrator formed by the integrating resister 8, the differential amplifier 11a and the integrating capacitor 9. In this case, since the voltage V, of the input terminal 10b is still maintained at the voltage V the drift of the differential amplifier lla can be effectively compensated. Accordingly, the integration of the input voltage can be performed without error caused by drift" in the integrator. In the above operation, if the drift voltages V and V are not varied, the gradient of the integrated output voltage V is irrespective of the drift voltages V and V so that drift" is completely eliminated from this integrating network. In this case, if an input voltage V, is applied across the input terminal 1 and the ground, an output voltage V having the gradient V lRC can be obtained at the output terminal 12.

In the drift memory circuit of the embodiment shown in FIG. 4, the switch 13 and the capacitor 14 may be provided before the d-c amplifier 19 as shown in FIG. 5. In this case, the charged voltage of the capacitor 14 is amplified at the d-c amplifier l9 and applied to the input terminal 10b of the differential amplifier lla through the connection line 18a. Other parts are the same as the parts of the embodiment shown in FIG. 4. In this embodiment, the dc amplifier 19 has to have a high impedance sufficient for avoiding a short-time discharge of the charged voltage of the capacitor 14. If the amplification factor n of the d-c amplifier 19 is sufficiently large, the above-mentioned Equation (3) is converted as follows:

Therefore, the drift voltages in the amplifiers Ila and I9 are effectively eliminated.

With reference to FIG. 6, a modification of the embodiment shown in FIG. 4 will be described. In this embodiment, a d-c amplifier 21 having an amplification factor u is provided between the switch 3 and the integrating resistance 8. Other parts are the same as the parts of the embodiment shown in FIG. 4.

In operation, the common terminal 7 of the switch 3 is connected to the terminal 4 while the switch 13 is switched-on. In this case. if it is assumed that respective drift voltages of the

amplifiers

21, 11a and I9 converted in terms of the respective [inputs] input terminals are a value V,, a value V; (at the input terminal 103) and a value V the output voltages V of the output terminal 12 is as follows:

Ifa condition u,u I is applied to the Equation (5 l, the following result is obtained.

In this case, if it is assumed that the voltage of the input terminal 10a is a value V the voltage of the input terminal 10b can be indicated as follows:

If conditions u u 1 and n I are applied to the Equation (7), the following result is obtained.

Therefore, no current flows in the resistor 8.

Thereafter, when the switch 13 is switched-off while the common terminal 7 of the switch 3 is connected to the terminal 5, an input voltage applied across the terminal l and the ground is integrated by an integrator formed by the d-c amplifier 21, the integrating resistor 8, the differential amplifier lla and the integrating capacitor 9. In this case, since the voltage V, of the input terminal 10b is still maintained at a voltage Vd equal to a voltage (V u V the drift voltages ofthe differential amplifier Ila and the d-c amplifier 21 can be effectively compensated. Accordingly, the integration of the input voltage can be performed without error caused by drift in the integrator. In the above operation, if the drift voltages V,, V and V are not varied, the gradient of the integrated output voltage V,, is irrespective of the drift voltages V,, V and V so that drift is completely eliminated from this integrating network. In this case, if an input voltage V is applied across the input terminal 1 and the ground, an output voltage V, having the gradient V /RC can be obtained.

In the drift memory circuit 20 of the embodiment shown in FIG. 6, the switch 13 and the capacitor 14 may be provided before the d-c amplifier I9 as shown in FIG. 7. In this case, the charged voltage of the capacitor 14 is amplified at the do amplifier l9 and applied to the input terminal 10b of the differential amplifier 11a through the connection line 18a. Other parts are the same as the parts of the embodiment shown in FIG. 6. In this embodiment, the d-c amplifier 19 has to have a high impedance sufficient for avoiding a short-time discharge of the charged voltage of the capacitor 14. If the amplification factor u of the amplifier 19 is sufficiently larger than one and also sufficiently larger than the amplification factor u of the amplifier 2], the above Equation (6) is converted as follows:

Therefore, the drift voltages in the amplifiers 21, Ila and 19 are effectively eliminated.

Each one of the above-mentioned integrating networks of this invention can be applied to form an analogue-digital converter in which an input signal is inte grated to detect the level of the input signal. A detailed discussion of the analogue-digital converter will follow after a description of how an error is caused by the drift in the integrator, described in view of the principle of the analogue-digital converter with reference to FIG. 8.

If it is assumed that the voltage of an input signal, a reference voltage and the time constant of the integrator are respectively values V V, and RC, an output wave form V,, having the gradient (-VJRC) is obtained at the output of the integrator in response to the voltage V of the input signal if the d-c amplifier employed in the integrator has no drift. In this case, if the input of the integrator is switched to the reference voltage V, at a time T, delayed by a time t, after a time T, when the output wave form V,, exceeds a predetermined reference level (e.g.; zero level Lo). the gradient of the output wave form V varies to a value V,,/RC so that the output waveform V reaches the zero level Lo at a time T, delayed by a time t, from the time T In this case. the following result is obtained.

Accordingly, the voltage V, of the input signal can be obtained from the values t lt, and V,,. This is the general principle of an analog-digital converter.

However. if the dc amplifier drifts, the output waveform Vo would reach a value (Vd.t,/RC) at a time T, even if the voltage V, of the input signal is zero; where the value Vd is a value of drift converted in terms of the input of the integrator. Accordingly, if the input voltage V, of the input signal is applied to the integrator having the drift Vd, the output wave form Vo has the gradient V, Vd)/RC. Therefore, if the input of the integrator is changed to the reference voltage V, at the time T, delayed by the time t, from the time T, when the output waveform Vo exceeds the zero level L0. The following error (t t results from the drift Vd.

FIG. 9 shows main parts of the analogue-digital converter using the integrating network of this invention to perform the above-mentioned principle without drift error." In this example, a terminal 6 is further provided at the switch 3 while a separated d-c source 22 is connected across the line 18 and the terminal 6. Other parts are the same as the integrating network shown in FIG. 2.

In operation, a linear wave form having the gradient V /RC is obtained at the output terminal 12 as an output voltage V,,, in a manner similar to the operation of the integrating network shown in FIG. 2. At a time T, delayed by a time t, from the time T, when the linear wave form exceeds a predetermined reference level (e.g.; zero level Lo), the terminal 6 and the terminal 7 are connected to each other at the switch 3 while the switch 13 is maintained at the switched-off condition. Since the polarity of the reference voltage V, is reverse to the polarity of the input voltage V,, a current i, which is obtained by dividing, by the resistance R of the resistor 8, the sum of the potential to the ground Vd of the line 18, the reference voltage V, of the reference d-c source 22 and the value of the drift Vd converted in terms of the input terminal of the integrator flows in the resistor 8. Namely:

Accordingly, a linear wave form having the gradient V,,/RC is obtained at the output terminal 12. At a time T delayed by a time t: from the time T the output voltage V reaches the zero level Lo. In this case, the relationship shown in the Equation is obtained. After the time T the switch I3 is switched-off while the terminal 4 and the terminal 7 are connected to each other at the switch 3 so that the above-mentioned stationary condition is obtained. Thereafter, these operations are repeated.

As understood from the above explanation. the relationship shown in the Equation (l0) can be obtained without error caused by "drift" even if the integrator has drift."

With reference to FIG. 10, an example of the analogue-digital converter provided with means for measuring the value t,/t shown in the Equation (l0) comprises

input terminals

1 and 2, a switch 3, an integrator 23, a switch 13, a drift member circuit 20, a reference d-c source 22, a zero-level detector 24 generating control pulses when the output voltage of the integrator 23 reaches a reference level (e.g.; zero level), a pulse generator 25 generating pulses at regular intervals, a counter 26 counting the number of the pulses applied from the pulse generator 25, and an output terminal 27.

In operation. if the drift voltage of the integrator 23 converted in terms of the input thereof is a value Vd when the switch 13 is switched-on while the terminal 4 is connected to the terminal 7, the output of the drift memory circuit 20 is maintained at a stationary value Vd. After an appropriate time in which the above stationary condition continues, the switch 13 is switchedoff while the terminal 5 is connected to the terminal 7 at the switch 3. Since the input voltage V,- is applied across the

terminals

1 and 2 and the potential to ground Vd is applied to the terminal 2 from the drift member circuit 20, the potential to ground of the input (e.g.; terminal 7) of the integrator 23 becomes a value V, V On the other hand, the drift voltage V,, of the integrator 23 converted in terms of the input thereof is a value V Accordingly, the output voltage V, of the integrator 23 obtained at the terminal 12 has the following gradient:

This output voltage V, is applied to the zero level detector 24, so that a first reset pulse is applied from the zero level detector 24 to the counter 26 at a time T, when the output voltage V, reaches the zero level Lo. In response to the first reset pulse, the counting state of the counter 26 is reset to a first counting state corresponding to a first number. Thereafter, the counter 26 counts the number of pulses from the pulse generator 25. When the counting state of the counter 26 reaches a second counting state corresponding to a second number, the counter 26 generates a second reset pulse which is applied to the switch 3 so as to switch the terminal 7 to the terminal 6. At the same time, the counter 26 is reset to zero. The second reset pulse is generated at the time T, delayed by the time t, from the time T,,. After the time T,, the voltage V, is applied across the line 18 and the terminal 7 so as to be reverse to the polarity of the input voltage V the output voltage V at the terminal 12 has the following gradient:

At the time T delayed by the time t from the T,. the output voltage V of the integrator 23 reaches the zero level Lo so that the zero level detector 24 generates a control signal. This control signal is applied to the switch 3 to switch the terminal 7 to the terminal 4 and to the switch 13 to switch it "on." The number of pulses counted in the counter 26 during the time t, is proportional to the input voltage V,. This counting result is obtained at the output terminal 27. In response to the switching of the

switches

3 and 13, the drift memory circuit 20 starts to detect and store the drift voltage Vd of the integrator 23, and the abovementioned operations are repeated.

Another embodiment of the integrating [networks network of this invention to be employed for providing an analogue-digital converter is described with reference to FIG. 11. In this embodiment, a d-c amplifier llb is further provided at the output of the integrator (8, 9 and lla). The output terminal 12 is provided at the output terminal of the d-c amplifier 11b, and the input of the drift memory circuit 20 is connected to the output terminal of the d-c amplifier llb. Moreover, a grounded terminal 6 is provided at the switch 3 and a reference voltage source 22 is connected across the terminal 4 of the switch 3 and ground. Other parts are the same as the parts of the embodiment shown in FIG. 4.

In operation, the common terminal 7 of the switch 3 is connected to the terminal 6 while the switch 13 is switched-on. In this case, if it is assumed that the respective drift voltages of the d-c amplifiers lla, llb and 19 converted in terms of the respective [inputs input terminals are values V,, V and V;,, the output voltage V of the output terminal 12 is as follows:

where references u u and u are respective amplification factors of the amplifiers 11a, llb and I9. lfa condition u,u u I is applied to the Equation (IS), the following result is obtained.

Therefore, a voltage V of the input terminal of the amplifier 11!) is indicated as follows:

If a condition u u u I is applied to the Equation [7), the following result is obtained.

Moreover, a voltage V 2 of the input terminal 10b of the amplifier I la is indicated as follows:

z zl trt a a l a s i i+ zl- If a condition u u u I is applied to the Equation (19), the following result is obtained.

Since the amplification factor u, is sufficiently larger than one, the following Equation (2|) is substantially satisfied.

Accordingly, no current flows in the resister 8. In this case, a quiescent condition is established. Thereafter, the switch 13 is switched-off and the terminal 7 of the switch 3 is switched to the terminal 5 to integrate, in the integrator (8, 9 and Ila), the input voltage V, applied across the terminal 5 and the ground. In this case, the integrator performs the integration of the input voltage V, without error caused by the drift of the amplifier lla as understood from the Equation (20). Moreover, the integrated result is obtained at the output terminal after amplification by the amplifier llb without error caused by the drift of the amplifier llb as understood from the Equation (18).

With reference to FIGS. 12 and 13, an example of the analogue-digital converter using the integrating network shown in FIG. 11 will be described. In addition to parts shown in FIG. 11, this example further comprises a multivibrator 24a reversing the state thereof when the output W2 of the amplifier llb intersects with a reference level 0, and a switching control circuit 28 for controlling the

switches

3 and 13 in response to control signals from the multivibrator 24a and the counter 26. The pulse generator 25 and the counter 26 are the same as the

circuits

25 and 26 of the example shown in FIG. 10. The d-c amplifier llb and the multivibrator 2421 form a zero-level detector 29.

In operation, a stationary condition is obtained in a condition where the switch 13 is switched-on and the common terminal 7 of the switch 3 is connected to the grounded terminal 6. At a time T the switch 13 is switched-off while terminal 7 is switched to the terminal 5 in response to the control signal supplied from the switch control circuit 28. Accordingly, a waveform W2 is obtained at the output terminal of the amplifier llb in response to the input signal V applied across the input terminal 1 and the ground. At a time T when the instantaneous level of the waveform w exceeds the zero-level O. the state of the multivibrator 24a is reversed. In response to the change of state of the multi vibrator 24a, the counter 26 starts to count the number of pulses from the pulse generator 25. At a time T delayed by a time t, from the time T,,, the counter 26 counts over n pulses so that the counter I: 26a] 26 is reset and generates a control signal which is applied through a line 33 to the switch control circuit 28. In response to the control signal from the counter 26, the switch control circuit 28 generates a control signal which is applied through a line 31 to the switch 3 so as to connect the terminal 7 to the terminal 4. Accordingly, the instantaneous level of the output signal of the amplifier llb is reduced and again intersects with the zero-level O at a time T delayed by a time t from the time T At the same time T the state of the multivibrator 24a is restored so that the counter 26 starts to count the number of pulses from the pulse generator 25 while the switch control circuit 28 switches off the switch 13 and switches the terminal 7 of the switch 3 to the terminal 6 to obtain the stationary condition. The counter 26 counts over m pulses during the time t,, and generates a digital output representative of the m pulses. After an appropriate time from the time T the switch control circuit 28 generates a control signal to switch-on the switch 13 and to switch the terminal 7 of the switch 3 to the terminal 5. Accordingly, the output wave form W2 is obtained at the output terminal 12 of the amplifier llb. As seen from the waveforms w and W2 in FIG. 12, the amplifier llb has a suflieiently high gain so that the amplifier llb is saturated at a low level ofthe output signal w, ofthe integrator. The abovementioned operations are repeated.

In accordance with the above-operations, the following result is obtained.

By way of example, if it is assumed that the time 1 is a time in which one thousand pulses are generated from the pulse generator, that the reference voltage V, of the reference d-c source 22 is l volt and that the counter 26 counts 542 pulses in the time t the value V, of the input signal is 0.542 volts.

if the input signal V,- has minus polarity, the polarity of the reference d-c voltage source 22 is also reversed so that plus terminal of the source 22 is connected to the terminal 4. The polarity of the output terminal of the d-c amplifier 11b may have the I: same] reverse polarity [as] to the input terminal of the amplifier llb. [n this case, the [phase] polarity relationship between the input and output terminals of the d-c amplifier I9 is I: also reversed the same polarity. in the drift memory circuit 20, the d-c amplifier 19 may be inserted in the line 18 so that the switch 13 is connected to the terminal 12 and the output terminal of the d-c amplifier 19 is connected to the input terminal 10b of the amplifier 11 through the line 18.

The embodiment shown in FIG. 11 can be modified as shown in FlG. 14 in which a d-c amplifier 21 is fur ther provided between the common terminal 7 and the integrating resistor 8. Other parts are the same as the embodiment shown in FIG. 11. A time chart explanatory ofthe operation of the example in FIG. 14 is shown in FIG. 15.

In operation, the common terminal 7 of the switch 3 is connected to the terminal 6 while the switch 13 is switched-on. in this case, if it is assumed that the respective drift voltages of the

d-c amplifiers

21, 1 la, 11b and 19 converted in terms of the respective [inputs input terminals are values V V V and V the output V,, of the output terminal 12 is as follows:

where references u,, u U3 and u are respective amplification factors of the

amplifiers

21, 11a, 11b and 19. if a condition u u u I is applied to the Equation (23 the following result is obtained.

Therefore, a voltage V of the input terminal 10b of the amplifier 11b is indicated as follows:

lf a condition u u u 1 and a condition u I are applied to the Equation (25), the following result is obtained.

Accordingly, no current flows in the integrating resistor 8. Moreover, a voltage V of the input terminal of the d-c amplifier 11b is indicated as follows:

a: 0 4 4 4 l l 2) 2 (2 If a condition u u u 1 is applied to the Equation [27), the following result is obtained.

As understood from the above equation, drift voltages of the d-c amplifiers 21,1la and 11b can be effectively eliminated in the embodiment shown in FIG. 14. In

other words, drift voltages of the preceding amplifier 21 and the succeeding amplifier 11b can be eliminated in addition to the drift voltage of the integrator (8, 9 and 11a).

The embodiment shown in FIG. 14 can be applied to form an analogue-digital converter as shown in FIG. 16. The operation of the analogue digital converter shown in H6. 16 can be understood in view of the operation of the analogue-digital converter shown in FIG. 13. Therefore, details are omitted while waveforms w and W2" are respective outputs of the amplifiers 11a and llb. As seen from the waveforms w and W2 in FIG. 15, the amplifier 11b has a sufficiently high gain so that the amplifier llh is saturated at a low level ofthe output signal W1 0f the integrator.

What I claim is:

1. An integrating network comprising:

an integrator having an output and having an input for receiving an input voltage signal, and being formed by a first d-c amplifier and time'constant means connected to said first d-c amplifier,

drift memory circuit means connected between the output and input of the integrator for feeding back in the opposite polarity] the output of the first d-c amplifier to [the] an input of the integrator in the absence of an input voltage at an input of the first d-c amplifier so as to obtain a stationary condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the stationary condition, the feedback signal having a value substantially equal to the drift voltage of the first d-c amplifier converted in terms of the input of the integrator,

whereby an input voltage signal is integrated in the integrator without error caused by the drift of the first d-c amplifier,

level detector means connected to the output of the integrator to produce a first control pulse when the output of the integrator exceeds a predetermined reference level and to produce a second control pulse when the output of the integrator crosses the predetermined reference level in the decreasing direction,

a time measuring means coupled to the level detector for generating a third control pulse in response to the termination of a predetermined first time period measured from the first control pulse and for measuring a second time period between the third control pulse and the second control pulse,

a reference d-c source, and

input switch means connected to said reference d-c source and to the input of the integrator for applying the input voltage signal to the integrator in response to the first control pulse, for applying a reference d-c voltage from the d-c source to the integrator in response to the third control pulse, and for shortening the input of the integrator in response to the second control pulse,

whereby the level of the input voltage signal can be determined by the ratio of the second time period to the first time period, multiplied by the value of the reference voltage from the reference d-c source.

2. An integrating network according to claim I, in which the drift memory circuit means comprises a second d-c amplifier, a switch connected to the output of the second d-c amplifier, means for actuating said switch to a closed state in the absence of said input voltage at the input of the first d-c amplifier and for actuating said switch to an open state upon application of the input voltage to the first d-c amplifier. and a capacitor connected in series between the switch and ground. 3. An integrating network according to claim 1, in which the drift memory circuit means comprises a switch, and means for actuating said switch to a switched-on state in the absence of said input voltage at the first d-c amplifier, and to a switched-off state at the application of the input voltage to the dc first amplifier, a capacitor connected between the switch and ground, and a second d-c amplifier connected to the junction between the switch and the capacitor.

4. An integrating network according to claim 1, in which the first d-c amplifier is a differential amplifier having a first input terminal receiving the input voltage signal to be integrated and a second input terminal receiving the feedback signal.

5. An integrating network, comprising: an integrator having an input and an output, and

being formed by a first d-c amplifier and timeconstant means connected to said first d-c amplifier, 1

a second d-c amplifier having an output connected to said input of the integrator, and having an input for the application of an input voltage signal thereto,

drift memory circuit means connected between the output and input of the integrator for feeding back [in the opposite polarity] the output of the first d-c amplifier to [the] an input of the integrator in the absence of said input voltage at an input of the second d-c amplifier so as to establish a quiescent condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the quiescent condition, the feedback signal having a value substantially equal to the drift voltages of the first and second d-c amplifiers converted in terms of the input of the integrator,

whereby said input voltage signal applied through the second d-c amplifier is integrated without error caused by the drift of the first and second d-c amplifiers.

6. An integrating network according to claim 5, in which the drift memory circuit means comprises a third d-c amplifier, a switch connected to the output of the third d-c amplifier, means for actuating said switch to a closed state in the absence of said input voltage at the input of the first d-c amplifier and for actuating said switch to an open state upon application of the input voltage to the first d-c amplifier, and a capacitor connected in series between the switch and ground.

7. An integrating network according to claim 5, in which the drift memory circuit means comprises a switch, and means for actuating said switch to a switchon state in the absence of said input voltage at the first d-c amplifier. and to a switched-off state at the application of the input voltage to the d-c first amplifier, a capacitor connected between the switch and ground, and a third d-c amplifier connected to the junction between the switch and the capacitor.

8. An integrating network according to claim 5, in which the first d-c amplifier is a differential amplifier having a first input terminal receiving the input voltage signal to be integrated and a second input terminal re ceiving the feedback signal.

9. An integrating network, comprising:

an integrator having an input and an output, and

being formed by a first d-c amplifier and timeconstant means connected to said first d-c amplifier,

a second d-c amplifier having an output connected to said input of the integrator, and

drift memory circuit means connected between the output and input of the integrator for feeding back I: in the opposite polarity the output of the first d-c amplifier to [the] an input of the integrator in the absence of an input voltage at an input of the second d-c amplifier so as to obtain a stationary condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the stationary condition, the feedback signal having a value substantially equal to the drift voltages of the first and second d-c amplifiers converted in terms of the input of the integrator,

whereby an input voltage signal applied through the second d-c amplifier is integrated without error caused by the drift of the first and second d-c amplifiers,

level detector means connected to the output of the integrator to produce a first control pulse when the output of the integrator exceeds a predetermined reference level and to produce a second control pulse when the output of the integrator crosses the predetermined reference level on the decreasing direction,

a reference d c source, and

input switch means connected to said reference d-c source and to the input of the second d-c amplifier for applying the input voltage signal to the second d-c amplifier in response to the first control pulse, for applying a reference d-c voltage from the d-c source to the second d-c amplifier in response to the third control pulse, and for shorting the input of the second d-c amplifier in response to the second control pulse,

whereby the level of the input voltage signal can be determined by the ratio of the second time period to the first time period, multiplied by the value of the reference voltage of the d-c source.

10. An integrating network, comprising:

an integrator having an input and an output, and

a second d-c amplifier having an input connected to said output of the integrator, and

drift memory circuit means connected between the output of the second amplifier and the input of the integrator for feeding back [in the opposite polarity] the output of the second dc amplifier to [the] an input of the integrator in the absence of an input voltage at the input of the first d-c amplifier so as to obtain a stationary condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the stationary condition, the fed back signal having a value substantially equal to the drift voltages of the first and second d-c amplifiers converted in terms of the input of the integrator,

whereby an input voltage is integrated in the integrator without error caused by the drift of the first and second d-c amplifiers so as to produce an integrated output of the input voltage at the output of the second amplifier.

level detector means connected to the output of the second d-c amplifier to produce a first control pulse when the output of the second d-c amplifier exceeds a predetermined reference level and to produce a second control pulse when the output of the second d-c amplifier crosses the predetermined reference level in the decreasing direction,

a reference d-c source, and

input switch means connected to said reference d-c source and to the input of the integrator for applying the input voltage signal to the integrator in response to the first control pulse, for applying a reference d-c voltage from the d-c source to the inte grator in response to the third control pulse, and for shorting the input of the integrator in response to the second control pulse,

whereby the level of the input voltage signal can be determined by the ratio of the second time period to the first time period, multiplied by the value of the reference voltage from the reference d-c source,

11. An integrating network, comprising:

an integrator having an input and an output, and

being formed by a first d-c amplifier and timeconstant means connected to the first d-c amplifier,

a second d-c amplifier having an output connected to said input of the integrator,

a third d-c amplifier having an input connected to the output of the integrator, and

drift memory circuit means connected between the output of the third amplifier and the input of the integrator for feeding back in the opposite polarity the output of the third d-c amplifier to [the] an input of the integrator in the absence of an input voltage at the input of the second d-c amplifier so as to obtain a stationary condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the stationary condition, the fed back signal having a value substantially equal to the drift voltages of the first, second and third d-c amplifiers converted in terms of the input of the integrator,

whereby an input voltage signal applied through the second d-c amplifier is integrated in the integrator without error caused by the drift of the first, second and third d-c amplifiers so as to produce an integrated output of the input voltage at the output of the third amplifier,

level detector means connected to the output of the third d-c amplifier to produce a first control pulse when the output of the third the amplifier exceeds a predetermined reference level and to produce a second control pulse when the output of the third d-c amplifier crosses the predetermined reference level in the decreasing direction,

a time measuring means coupled to the level detector for generating a third control pulse in response to the termination of a predetermined first time per iod measured from the first control pulse and for measuring a second time period between the third control pulse and the second control pulse,

a reference d-c source, and

input switch means connected to said reference d-c source and to the input of the second d-c amplifier for applying the input voltage signal to the second d-c amplifier in response to the first control pulse, for applying a reference d-c voltage from the dc source to the second d-c amplifier in response to the third control pulse, and for shorting the input of the second d-c amplifier in response to the second control pulse,

12. An integrating network, comprising:

an integrator having an input and an output, and

drift memory circuit means connected between the output of the second amplifier and the input of the integrator for feeding back [in the opposite polarity] the output of the second d-c amplifier to [the] an input of the integrator in the absence of an input voltage at the input of the first d-c amplifier so as to obtain a stationary condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the stationary condition, the fed back signal having a value substantially equal to the drift voltages of the first and second d-c amplifiers converted in terms of the input of the integrator,

whereby an input voltage is integrated in the integrator without error caused by the drift of the first and second d-c amplifiers so as to produce an integrated output of the input voltage at the output of the second amplifier,

13. An integrating network according to claim 12, in which the drift memory circuit means comprises a third d-c amplifier, a switch connected to the output of the third d-c amplifier, means for actuating said switch to a closed state in the absence of said input voltage at the input of the first d c amplifier and for actuating said switch to an open state upon application of the input voltage to the first d-c amplifier, and a capacitor connected in series between the switch and ground.

14. An integrating network according to claim 12, in which the drift memory circuit means comprises a switch, and means for actuating said switch to a switched-on state in the absence of said input voltage at the first d-c amplifier, and to a switched-off state at the application of the input voltage to the first d-c amplifier, a capacitor connected between the switch and ground, and a third d-c amplifier connected to the junction between the switch and the capacitor.

15. An inte rating network according to claim 12, in which the fcomprising an integrator having an input terminal and an output terminal and being formed by a first d-c amplifier and time-constant means connected to the first d-c amplifier, said first d-c amplifier I: is] being a differential amplifier having a first input terminal receiving [the] an input voltage signal to be integrated and a second input terminal, [receiving the feedback signal] a second d-c amplifier having an input terminal connected to the output terminal of the integrator,

drift memory circuit means connected between an output terminal ofsaid second d-c amplifier and the second input terminal of said differential amplifier for feeding back the output of the second d-c amplifier to said second input terminal of said differential amplijier in the absence of said input voltage signal at the input terminal ofthe integrator so as to establish a quiescent condition, the feedback signal having a value substantially equal to the drift voltage of the first and second d-c amplifier converted to terms of the first input terminal of said differential amplifier,

whereby said input voltage signal is integrated in the integrator without error caused by the drift of the first and second d-c amplifier so as to produce an integrated and amplified output of the input voltage at the output terminal of the second amplifier.

16. An integrating network, comprising:

an integrator having an input and an output, and

being formed by a first d-c amplifier and timeconstant means connected to the first cl-c amplifier,

a second d-c amplifier having an output connected to said input of the integrator, and having an input for the application of an input voltage signal,

a third d-c amplifier having an input connected to the output of the integrator, and drift memory circuit means connected between the output of the third amplifier and the input of the integrator for feeding back in the opposite polarity] the output of the third d-c amplifier to [the] an input of the integrator in the absence of said input voltage at the input of the' second d-c amplifier so as to establish a quienscent condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the quiescent condition, the fed back signal having a value substantially equal to the drift voltages of the first, second and third d-c amplifiers converted in terms of the input of the integrator,

whereby said input voliage signal applied through the second d-c amplifier is integrated in the integrator without error caused by the drift of the first, second and third d-c amplifiers so as to produce an integrated output of the input voltage at the output of the third amplifier.

17. An integrating network according to claim 16, in which the drift memory circuit means comprises a fourth d-c amplifier, a switch connected to the output of the fourth d-c amplifier, means for actuating said switch to a closed state in the absence of said input voltage at the input of the first d-c amplifier and for actuating said switch to an open state upon application of the input voltage to the first d-c amplifier, and a capacitor connected in series between the switch and ground.

18. An integrating network according to claim 16, in which the drift memory circuit means comprises a switch, and means for actuating said switch to a switched-on state in the absence of said input voltage at the first d-c amplifier, and to a switched-off state at the application of the input voltage to the d-c first amplifier, a capacitor connected between the switch and ground, and a fourth d-c amplifier connected to the junction between the switch and the capacitor.

19. An integrating network [according to claim 16, in which the] comprising an integrator having an input terminal and an output terminal and being formed by a first d-c amplifier and time-constant means connected to the first d-c amplifier,

a second d-c amplifier having an output terminal connected to said input terminal of the integrator and an input terminalfor the application ofan input voltage signal, said first d-c amplifier [is] being a differential amplifier having a first input terminal receiving the input voltage signal [to be integrated receiving, through said second d-c amplifier, said input voltage signal and a second input terminal, [receiving the feedback signal] third d-c amplifier having an input terminal connected to the output terminal of the integrator,

drift memory circuit means connected between an output terminal ofsaid third d-c amplifier and the sec and input terminal of said differential amplifier for feeding back the output of the third d-c amplifier to said second input terminal ofsaid differential amplifier in the absence ofsaid input voltage signal at the input terminal of the second d-c amplifier so as to establish a quiescent condition and for continuously sending out, as afeedback signal, a voltage fed back to said second input terminal ofsaid differential am plifier at the quiescent condition, the feedback signal having a value substantially equal to the drift voltage ofthe first, second and third amplifiers converted in terms of the first input terminal of said differential amplifier,

whereby said input voltage signal applied through the second d-c amplifier is integrated in the integrator without error caused by the drift of the first, second and third d-c amplifiers so as to produce an integrated and amplified output of the input voltage at the output terminal of the third amplifier.

20. An integrating network according to claim I5, in which said second d-c amplifier is saturable at a low level of the output of said integrator.

21. An integrating network according to claim 19, in which said second d-c amplifier is saturable at a low level of the output of said integrator.

UNITED STATES PATENT OFFICE QERTIFICATE OF CORRECTION PATENT NO. 2 Re. 28,579

DATED Reissued Oct. 21, 1975 INVENTOR(S) 1 Kozo Uchida It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Column ll, line 20, delete "ll" and insert --lla-;

Column 17, line 46, delete "fed back" and insert --feedback--;

Column 18, line 56, delete "second" and insert -third--.

Signed and Scaled this eighth Day of June 1976 [SEAL] Arrest:

RUTH C. MASON C. MARSHALL DANN m?" I fimnlimoner oj'Pamm and Trademark:

Claims

1. An integrating network comprising: an integrator having an output and having an input for receiving an input voltage signal, and being formed by a first d-c amplifier and time-constant means connected to said first d-c amplifier, drift memory circuit means connected between the output and input of the integrator for feeding back (in the opposite polarity) the output of the first d-c amplifier to (the) an input of the integrator in the absence of an input voltage at an input of the first d-c amplifier so as to obtain a stationary condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the stationary condition, the feedback signal having a value substantially equal to the drift voltage of the first d-c amplifier converted in terms of the input of the integrator, whereby an input voltage signal is integrated in the integrator without error caused by the drift of the first d-c amplifier, level detector means connected to the output of the integrator to produce a first control pulse when the output of the integrator exceeds a predetermined reference level and to produce a second control pulse when the output of the integrator crosses the predetermined reference level in the decreasing direction, a time measuring means coupled to the level detector for generating a third control pulse in response to the termination of a predetermined first time period measured from the first control pulse and for measuring a second time period between the third control pulse and the second control pulse, a reference d-c source, and input switch means connected to said reference d-c source and to the input of the integrator for applying the input voltage signal to the integrator in response to the first control pulse, for applying a reference d-c voltage from the d-c source to the integrator in response to the third control pulse, and for shortening the input of the integrator in response to the second control pulse, whereby the level of the input voltage signal can be determined by the ratio of the second time period to the first time period, multiplied by the value of the reference voltage from the reference d-c source.

2. An integrating network according to claim 1, in which the drift memory circuit means comprises a second d-c amplifier, a switch connected to the output of the second d-c amplifier, means for actuating said switch to a closed state in the absence of said input voltage at the input of the first d-c amplifier and for actuating said switch to an open state upon application of the input voltage to the first d-c ampLifier, and a capacitor connected in series between the switch and ground.

3. An integrating network according to claim 1, in which the drift memory circuit means comprises a switch, and means for actuating said switch to a switched-on state in the absence of said input voltage at the first d-c amplifier, and to a switched-off state at the application of the input voltage to the d-c first amplifier, a capacitor connected between the switch and ground, and a second d-c amplifier connected to the junction between the switch and the capacitor.

5. An integrating network, comprising: an integrator having an input and an output, and being formed by a first d-c amplifier and time-constant means connected to said first d-c amplifier, a second d-c amplifier having an output connected to said input of the integrator, and having an input for the application of an input voltage signal thereto, drift memory circuit means connected between the output and input of the integrator for feeding back (in the opposite polarity) the output of the first d-c amplifier to (the) an input of the integrator in the absence of said input voltage at an input of the second d-c amplifier so as to establish a quiescent condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the quiescent condition, the feedback signal having a value substantially equal to the drift voltages of the first and second d-c amplifiers converted in terms of the input of the integrator, whereby said input voltage signal applied through the second d-c amplifier is integrated without error caused by the drift of the first and second d-c amplifiers.

7. An integrating network according to claim 5, in which the drift memory circuit means comprises a switch, and means for actuating said switch to a switch-on state in the absence of said input voltage at the first d-c amplifier, and to a switched-off state at the application of the input voltage to the d-c first amplifier, a capacitor connected between the switch and ground, and a third d-c amplifier connected to the junction between the switch and the capacitor.

8. An integrating network according to claim 5, in which the first d-c amplifier is a differential amplifier having a first input terminal receiving the input voltage signal to be integrated and a second input terminal receiving the feedback signal.

9. An integrating network, comprising: an integrator having an input and an output, and being formed by a first d-c amplifier and time-constant means connected to said first d-c amplifier, a second d-c amplifier having an output connected to said input of the integrator, and drift memory circuit means connected between the output and input of the integrator for feeding back (in the opposite polarity) the output of the first d-c amplifier to (the) an input of the integrator in the absence of an input voltage at an input of the second d-c amplifier so as to obtain a stationary condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the stationary condition, the feedback signal havIng a value substantially equal to the drift voltages of the first and second d-c amplifiers converted in terms of the input of the integrator, whereby an input voltage signal applied through the second d-c amplifier is integrated without error caused by the drift of the first and second d-c amplifiers, level detector means connected to the output of the integrator to produce a first control pulse when the output of the integrator exceeds a predetermined reference level and to produce a second control pulse when the output of the integrator crosses the predetermined reference level in the decreasing direction, a time measuring means coupled to the level detector for generating a third control pulse in response to the termination of a predetermined first time period measured from the first control pulse and for measuring a second time period between the third control pulse and the second control pulse, a reference d-c source, and input switch means connected to said reference d-c source and to the input of the second d-c amplifier for applying the input voltage signal to the second d-c amplifier in response to the first control pulse, for applying a reference d-c voltage from the d-c source to the second d-c amplifier in response to the third control pulse, and for shorting the input of the second d-c amplifier in response to the second control pulse, whereby the level of the input voltage signal can be determined by the ratio of the second time period to the first time period, multiplied by the value of the reference voltage of the d-c source.

10. An integrating network, comprising: an integrator having an input and an output, and being formed by a first d-c amplifier and time-constant means connected to said first d-c amplifier, a second d-c amplifier having an input connected to said output of the integrator, and drift memory circuit means connected between the output of the second amplifier and the input of the integrator for feeding back (in the opposite polarity) the output of the second d-c amplifier to (the) an input of the integrator in the absence of an input voltage at the input of the first d-c amplifier so as to obtain a stationary condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the stationary condition, the fed back signal having a value substantially equal to the drift voltages of the first and second d-c amplifiers converted in terms of the input of the integrator, whereby an input voltage is integrated in the integrator without error caused by the drift of the first and second d-c amplifiers so as to produce an integrated output of the input voltage at the output of the second amplifier, level detector means connected to the output of the second d-c amplifier to produce a first control pulse when the output of the second d-c amplifier exceeds a predetermined reference level and to produce a second control pulse when the output of the second d-c amplifier crosses the predetermined reference level in the decreasing direction, a time measuring means coupled to the level detector for generating a third control pulse in response to the termination of a predetermined first time period measured from the first control pulse and for measuring a second time period between the third control pulse and the second control pulse, a reference d-c source, and input switch means connected to said reference d-c source and to the input of the integrator for applying the input voltage signal to the integrator in response to the first control pulse, for applying a reference d-c voltage from the d-c source to the integrator in response to the third control pulse, and for shorting the input of the integrator in response to the second control pulse, whereby the level of the input voltage signal can be determined by the ratio of the second time period to the first time period, multiplieD by the value of the reference voltage from the reference d-c source.

11. An integrating network, comprising: an integrator having an input and an output, and being formed by a first d-c amplifier and time-constant means connected to the first d-c amplifier, a second d-c amplifier having an output connected to said input of the integrator, a third d-c amplifier having an input connected to the output of the integrator, and drift memory circuit means connected between the output of the third amplifier and the input of the integrator for feeding back (in the opposite polarity) the output of the third d-c amplifier to (the) an input of the integrator in the absence of an input voltage at the input of the second d-c amplifier so as to obtain a stationary condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the stationary condition, the fed back signal having a value substantially equal to the drift voltages of the first, second and third d-c amplifiers converted in terms of the input of the integrator, whereby an input voltage signal applied through the second d-c amplifier is integrated in the integrator without error caused by the drift of the first, second and third d-c amplifiers so as to produce an integrated output of the input voltage at the output of the third amplifier, level detector means connected to the output of the third d-c amplifier to produce a first control pulse when the output of the third d-c amplifier exceeds a predetermined reference level and to produce a second control pulse when the output of the third d-c amplifier crosses the predetermined reference level in the decreasing direction, a time measuring means coupled to the level detector for generating a third control pulse in response to the termination of a predetermined first time period measured from the first control pulse and for measuring a second time period between the third control pulse and the second control pulse, a reference d-c source, and input switch means connected to said reference d-c source and to the input of the second d-c amplifier for applying the input voltage signal to the second d-c amplifier in response to the first control pulse, for applying a reference d-c voltage from the d-c source to the second d-c amplifier in response to the third control pulse, and for shorting the input of the second d-c amplifier in response to the second control pulse, whereby the level of the input voltage signal can be determined by the ratio of the second time period to the first time period, multiplied by the value of the reference voltage from the reference d-c source.

12. An integrating network, comprising: an integrator having an input and an output, and being formed by a first d-c amplifier and time-constant means connected to said first d-c amplifier, a second d-c amplifier having an input connected to said output of the integrator, and drift memory circuit means connected between the output of the second amplifier and the input of the integrator for feeding back (in the opposite polarity) the output of the second d-c amplifier to (the) an input of the integrator in the absence of an input voltage at the input of the first d-c amplifier so as to obtain a stationary condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the stationary condition, the fed back signal having a value substantially equal to the drift voltages of the first and second d-c amplifiers converted in terms of the input of the integrator, whereby an input voltage is integrated in the integrator without error caused by the drift of the first and second d-c amplifiers so as to produce an integrated output of the input voltage at the output of the second amplifier.

13. An integrating network according to claim 12, in which the drift memory circuit means comprises a third d-c amplifier, a switch connected to the output of the third d-c amplifier, means for actuating said switch to a closed state in the absence of said input voltage at the input of the first d-c amplifier and for actuating said switch to an open state upon application of the input voltage to the first d-c amplifier, and a capacitor connected in series between the switch and ground.

15. An integrating network (according to claim 12, in which the) comprising an integrator having an input terminal and an output terminal and being formed by a first d-c amplifier and time-constant means connected to the first d-c amplifier, said first d-c amplifier (is) being a differential amplifier having a first input terminal receiving (the) an input voltage signal to be integrated and a second input terminal, (receiving the feedback signal) a second d-c amplifier having an input terminal connected to the output terminal of the integrator, drift memory circuit means connected between an output terminal of said second d-c amplifier and the second input terminal of said differential amplifier for feeding back the output of the second d-c amplifier to said second input terminal of said differential amplifier in the absence of said input voltage signal at the input terminal of the integrator so as to establish a quiescent condition, the feedback signal having a value substantially equal to the drift voltage of the first and second d-c amplifier converted to terms of the first input terminal of said differential amplifier, whereby said input voltage signal is integrated in the integrator without error caused by the drift of the first and second d-c amplifier so as to produce an integrated and amplified output of the input voltage at the output terminal of the second amplifier.

16. An integrating network, comprising: an integrator having an input and an output, and being formed by a first d-c amplifier and time-constant means connected to the first d-c amplifier, a second d-c amplifier having an output connected to said input of the integrator, and having an input for the application of an input voltage signal, a third d-c amplifier having an input connected to the output of the integrator, and drift memory circuit means connected between the output of the third amplifier and the input of the integrator for feeding back (in the opposite polarity) the output of the third d-c amplifier to (the) an input of the integrator in the absence of said input voltage at the input of the second d-c amplifier so as to establish a quienscent condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the quiescent condition, the fed back signal having a value substantially equal to the drift voltages of the first, second and third d-c amplifiers converted in terms of the input of the integrator, whereby said input voltage signal applied through the second d-c amplifier is integrated in the integrator without error caused by the drift of the first, second and third d-c amplifiers so as to produce an integrated output of the input voltage at the output of the third amplifier.

19. An integrating network (according to claim 16, in which the) comprising an integrator having an input terminal and an output terminal and being formed by a first d-c amplifier and time-constant means connected to the first d-c amplifier, a second d-c amplifier having an output terminal connected to said input terminal of the integrator and an input terminal for the application of an input voltage signal, said first d-c amplifier (is) being a differential amplifier having a first input terminal receiving the input voltage signal (to be integrated) receiving, through said second d-c amplifier, said input voltage signal and a second input terminal, (receiving the feedback signal) a third d-c amplifier having an input terminal connected to the output terminal of the integrator, drift memory circuit means connected between an output terminal of said third d-c amplifier and the second input terminal of said differential amplifier for feeding back the output of the third d-c amplifier to said second input terminal of said differential amplifier in the absence of said input voltage signal at the input terminal of the second d-c amplifier so as to establish a quiescent condition and for continuously sending out, as a feedback signal, a voltage fed back to said second input terminal of said differential amplifier at the quiescent condition, the feedback signal having a value substantially equal to the drift voltage of the first, second and third amplifiers converted in terms of the first input terminal of said differential amplifier, whereby said input voltage signal applied through the second d-c amplifier is integrated in the integrator without error caused by the drift of the first, second and third d-c amplifiers so as to produce an integrated and amplified output of the input voltage at the output terminal of the third amplifier.

20. An integrating network according to claim 15, in which said second d-c amplifier is saturable at a low level of the output of said integrator.