US3300631A - Analog multiplier - Google Patents

Description

Jan. 24, 1967 L. M. VALLI-:SE

ANALOG MULTIPLIER Filed April 17, 1963 @Ik vos S9@ m; n wovk; wwm m INVENTOR.

M. VAL ESE LUC/O AGENT United States Patent Otice Patented Jan. 24g, 1967 3,300,631 ANALOG MULTIPLIER Lucio-M. Vallese, Glen Ridge, NJ., assignor to International Telephone and Telegraph Corporation, Nutley, N .I a corporation of Maryland Filed Apr. 17, 1963, Ser. No. 273,663 8 Claims. (Cl. 23S-194) This invention relates to analog multipliers and more particularly to an improved :analog multiplier for multiplying the instantaneous values of -two electrical signals.

Analog multipliers, such as employed in analog cornputers, have in the past employed elaborate circuitry, for instance, servo mechanisms, function generators, or phase modulators. These prior art analog -computers have two limitations, namely, the signals to be multiplied must be D.C. or slowly varying A.C. signals and the bandwidth is restricted.

An object of this invention is the provision of simple circuitry to multiply the instantaneous values of two varying electrical signals w-hose operation is independent ofthe frequency yrange of the signals, at least within the frequency range limitation of the external components of the circuit.

Another object of this invention is lto provide a transistor circuit to multiply the instantaneous value of two varying electrical -signals and provide a voltage output proportional to either the instantaneous product of the two signals or a time average product of the two signals.

A feature of this invention is the provision of a transistor amplifier of the complementary symmetry transistor type wherein the signal controlling the collector current to be proportional thereto is coupled to the collector electrode to provide the product of the instantaneous value of the tw-o electrical signals or the time average product thereof.

The above-mentioned and other features and objects of this invention will become more apparent by reference to the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic diagram of an embodiment of an :analog multiplier according to this invention; and

FIG. 2 is a series of curves illustrating the multiplier characteristics of the embodiment of FIG. l.

The operation of the multiplier in accordance with this invention is based on the particular characteristic of transistors, namely, that the transconduotance, gm, is directly proportional to the collector current. This may be illustrated as follows. Theoretically q gm kT(IoIcs) where q is equal to the magnitude of electronic charge, k is equal -to the Boltzmann constant (1.381 l23 joule/ K. T equals the temperature in degree Kelvin, Ic equals the collector current, and Ics equals the inverse collector saturation current. For the practical operation of the 'analog multiplier of this invention, the inverse collector saturation current, ICS, is negligible and, thus, the Equation l will reduce to gm=kl1c (2) where k1 is equal to q/kT which is equal to 38.4 at a room temperature of 25 C. (centigrade). If itis desired to perform the multiplication of two signals, of the alternating type and obtain a product of these two signals, vlvz, a transistor amplifier is constructed in which the input signal applied to the input electrode is proportional to v1 and the collector current is rendered proportional to v2, The resulting output voltage will contain a term proportional to vlvz.

Referring to FIG. 1, there is illustrated therein a schematic diagram of a preferred embodiment of an analog multiplier according to this invention. This multiplier includes two complementary symmetry transistors 30- and 31 biased for class B operation with :a common collector terminal 32. The two voltages or signals v1 and v2 to be multiplied are applied respectively to the base electrodes of transistors 30 and 31 through coupling condensers 33 and 34 and to the collector electrodes of transistors 30 and 41 through resistor 3S. In this circuit arrangement the collector current of transistors 30 and 31 is varied by the voltage v2 applied to the common collector terminal 32 and the output voltage will include la voltage proportional to vlvz. When this is applied to an integrator circuit 36, the time average of the product v1v2 is obtained. If the input voltages v1 and v2 are sinusoidal, the output voltage at terminal 37 will be non-zero if, and only if, these two input voltages v1 and v2 have the same frequency. The output may be expressed as follows starting with Equation 3.

vout=ymRLviu (3) q vaut-ICTRLIcvm Letting vm:Vb-{v1 where Vb() is a constant and equal to the bias voltage,

where V1 and V2 are the amplitudes of the two voltages and o is their relative phase difference. It should be noted that the resulting voltage is generally very small due to the tact that rd is large.

In the case in which the voltage v2 is not of the alternating type, the output from terminal 32 must be processed through ya difference amplifier, the other input to the dillerence amplifier ibeing the signal v2 in order to cancel out the term proportional to v2 from the output signal veut. Difference amplifiers suitable for this application are well known in the art and therefore a detailed discussion thereof is not deemed necessary herein.

The operation of the multiplier is valid within certain linite ranges of the input voltages. An example of linearity of multiplier operation is shown in FIG. 2 where the output voltage is plotted versus one of v1 and v2, keeping the other signal constant. As illustrated v1 is maintained constant and v2 is varied. The correct operation of the multiplier of FIG. l corresponds to the ranges of v1 and v2 for which the output is represented by the solid straight lines with slope linearly proportional to the Variable parameter.

The component values for the reduction to practice of FIG. 1 are listed below.

R1:500K ohms R2: 15K ohms R3:l.6K ohms R4: 100K ohms R5:6.8K ohms R6:1..6K ohms R7:1OK ohms R8:1O0K ohms C1:27 microfarads C2:27 microfarads C3:l microfarad 3 +B= volts 3:10 volts Transistor 30+2N1415 Transistor 31: 2N l 694 While I have described ,above the principles of my invention in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a :limitation to the scope of my invention :as set forth in the objects thereof and in the accompanying claims.

I claim:

1. An analog multiplier for two electrical signals comprising:

a transistor amplier including two complementary symmetry transistors, each having `at least base, emitter and coslllector electrodes;

rst means to couple a rst of said signals to said base electrode of each transistor, the signal appearing at each of said base electrodes being -substantially the same;

second means to couple the second of said signals to said collector electrodes of each transistor to control 4the collector current of said transistors to be proportional to said second signal; and

out-put mean-s coupled to said collector electrode of each of said transistors to provide an -output voltage proportional to the product of said two signals.

2. The `analog multiplier according to claim 1 wherein said out-put means includes an integrator coupled to said collector electrodes of each of said transistors to provide an output voltage proportional to the time average product of said two signals.

3. The analog multiplier according to claim 2 wherein said integrator comprises:

a rst resistor coupled to the collector electrodes of said transistors; 'and a capacitor coupled to `said lirst resistor, the output signal being obtained at the connection between said iirst resistor and said capacit-or.

4. The analog multiplier according to claim 1 wherein said rst means comprises rst land second capacitors coupling said first signal to said base electrodes of each of said transistors, respectively.

5. The analog multiplier according to claim 1 wherein said second means comprises a second resistor coupling said second signal to said collector electrodes of said transistors. l

6. The analog multiplier iaccording to claim 1 further comprising means for bia-sing said transistor for class AB operation.

7. The analog multiplier according to claim 1 further comprising:

means coupling said collector electrodes together; and

means coupling said emitter electrodes together.

8. The analog multiplier according to claim 7 wherein said colt-lector electrodes are directly 4connected together and wherein said emitter electrodes are directly connected together.

References Cited by the Examiner UNITED STATES PATENTS 2,891,726 6/1959 Decker et al 235--194 3,010,069 ll/l96l Mi=lls et all. s 235-l94 X 3,202,807 8/1965 Sikorra 235-194 3,219,808 ll/l965 Lee 23S-194 MALCOLM A. MORRISON, Primary Examiner.

K. W. DOBYNS, Assistant Examiner.

Claims (1)

1. AN ANALOG MULTIPLIER FOR TWO ELECTRICAL SIGNALS COMPRISING: A TRANSISTOR AMPLIFIER INCLUDING TWO COMPLEMENTARY SYMMETRY TRANSISTORS, EACH HAVING AT LEAST BASE, EMITTER AND COLLECTOR ELECTRODES; FIRST MEANS TO COUPLE A FIRST OF SAID SIGNALS TO SAID BASE ELECTRODE OF EACH TRANSISTOR, THE SIGNAL APPEARING AT EACH OF SAID BASE ELECTRODES BEING SUBSTANTIALLY THE SAME; SECOND MEANS TO COUPLE THE SECOND OF SAID SIGNALS TO SAID COLLECTOR ELECTRODES OF EACH TRANSISTOR TO CONTROL THE COLLECTOR CURRENT OF SAID TRANSISTORS TO BE PROPORTIONAL TO SAID SECOND SIGNAL; AND OUTPUT MEANS COUPLED TO SAID COLLECTOR ELECTRODE OF EACH OF SAID TRANSISTORS TO PROVIDE AN OUTPUT VOLTAGE PROPORTIONAL TO THE PRODUCT OF SAID TWO SIGNALS.

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