JPH06208424A - Function generating circuit - Google Patents

Abstract

PURPOSE:To obtain a square output of an input signal by impressing input voltage with mutually inverted phases to an input and impressing the input voltage with mutually inverted phases also to gate voltage by using a MOS transistor(TR) capable of controlling a resistance value by the gate voltage as a resistor in an adder using a resistor and an operational amplifier. CONSTITUTION:A MOS TR 3 for a feedback resistor is connected between the inverted input terminal of an operational amplifier 4 and an output. The sources of MOS TRs 1, 2 are connected to the inverted input terminal in common, a positive phase input signal and an inverted phase input signal are respectively applied to the drains of the TRs 1, 2 and the inverted phase input signal and the positive phase input signal are respectively applied to their gates.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a C used in a system for displaying images or characters such as televisions and computers.
Used in the distortion correction circuit of RT deflection current, especially M
The present invention relates to a function generating circuit suitable for being implemented as an OS type semiconductor integrated circuit device.

[0002]

2. Description of the Related Art Conventionally, as a distortion correction circuit for CTE deflection current, for example, as shown in “NHK Television Technology Textbook (above)” edited by Japan Broadcasting Corporation, P.233-P.234 (1989), A circuit method has been known in which resonance of a coil and a capacitor is used to obtain a square waveform (parabolic waveform) as a distortion correction waveform.

[0003]

Unlike a television, a CRT display monitor such as a personal computer or a workstation may have several kinds of deflection frequencies. In this case, the conventional circuit system described above is accompanied by a change in deflection frequency. However, the amplitude of the distortion correction waveform changes. Further, since the deflection frequency is detected, the switch is switched by the detected output, and the constant such as the capacitor is switched, a large number of individual components are used, which is not suitable for an integrated circuit.

On the other hand, the required amplitude of the distortion correction waveform is determined by the shape of the tube surface of the CRT used, and a constant amplitude is required regardless of changes in the deflection frequency. The present invention provides a circuit that is suitable for integration into an integrated circuit and that generates a distortion correction waveform with a constant amplitude regardless of changes in the deflection frequency.

[0005]

The present invention provides two MOSs.
The source electrode of the transistor is commonly connected to the inverting input terminal of the operational amplifier, the output terminal of the operational amplifier is connected to the inverting input terminal with a resistor, an input signal is applied to the drain of one MOS transistor, and the remaining one MOS transistor In a so-called adder circuit that applies the waveform of the input signal of opposite polarity to the drain of, the source voltage and the drain resistance of the MOS transistor are changed in proportion to the input by setting the gate voltage of the two MOS transistors as a waveform similar to the input signal waveform. Thus, the squared waveform of the input waveform is obtained.

[0006]

According to the present invention, the amplitude of the squared waveform, that is, the distortion correction waveform is influenced only by the amplitude of the input waveform and is not dependent on the frequency.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS. In FIG. 1, the drain electrode of the MOS transistor 1 is connected to the positive input terminal, and the source electrode is connected to the inverting input terminal of the operational amplifier 4. The drain electrode of the MOS transistor 2 is connected to the negative input terminal, and the source electrode 4 is commonly connected to the inverting input terminal of the operational amplifier 4. Here, a signal −V _in having the opposite polarity of the input signal V _in applied to the positive input terminal is applied to the negative input terminal. The non-inverting input terminal of the operational amplifier 4 is at the reference potential, and the output terminal is MO.
It is connected to the source electrode of the S transistor 3. MO
The drain electrode of the S transistor 3 is connected to the inverting input terminal of the operational amplifier 4. Since the gate voltage of the MOS transistor 3 is connected to the fixed voltage V _G , M
The OS transistor 3 has the same function as the constant resistance. Therefore, the MOS transistor 3 can be replaced with a resistor.

When a waveform similar to the input signal V _in is V _a and the ground potential is V _G , a voltage of V _G -V _a is applied to the gate electrode of the MOS transistor 1 and V _G is applied to the gate electrode of the MOS transistor 2. A voltage of _G + V _a is applied. First, the input / output characteristics of the circuit will be described below.

The gates of the MOS transistors 1, 2, 3
The source-to-source voltages are V _GS1 , V _GS2 , and V _GS3 , the threshold voltage is V _TH , and the voltage-current conversion coefficient of the MOS transistor is K.
And When the drain-source voltage of the MOS transistor is sufficiently small, the resistance R _{1 of the} MOS transistor
~ R ₃ is generally R ₁ = 1 / {K · (V _GS1 − V _TH )}, R ₂ = 1 / {K · (V _GS2 − V _TH )} _, R ₃ = 1 / {K · (V _GS3 -V _TH )} is represented by (1).

On the other hand, the input / output characteristic of the circuit of FIG. 1 can be expressed by the following formula: V _in / R ₁ -V _in / R ₂ = -V _out / R ₃ (2), which is generally called an adder. Substituting Eq. (1) into Eq. (2), V _in · K · {(V _GS1 -V _TH )-(V _GS2 -V _TH )} = -K · (V _GS3 -V _TH ) · V _out … (3) Here, since V _GS1 = V _G- V _a, V _GS2 = V _{G +} V _a, V _GS3 = V _G , substituting, 2 · V _in · V _a = (V _G- V _TH ). V _out (4) V _a is _a waveform similar to V _in , and its proportional coefficient is α. V _in ² = (V _G- V _TH ) V _out (5) That is, the output is input. The squared waveform of is obtained.

FIG. 2 shows the waveform of each part in the circuit of FIG. Here, V _in increases linearly or decreases linearly with the passage of time. V _a is V _in
Is multiplied by _a proportional coefficient α, V _G + V _a is between the gate and source of the MOS transistor 2, and V _G −V _a is MOS.
It is added between the gate and the source of the transistor 1.
The output voltage V _out is made with increasing section of the input V _in, the square wave in accordance with the respective falling section. Here, the output amplitude depends only on the input voltage, as is clear from Eq. (5), and is independent of frequency and slope.

A second embodiment of the present invention will be described with reference to FIGS. In the circuit of FIG. 3, the MOS transistor 1,
The part consisting of 2, 3 and the operational amplifier 4 is the same as the circuit of FIG. The front part is resistors 5, 6, 7, 8, 9, 10,
Voltage dividing circuit composed of 11 and 12, and operational amplifier 2
7, 28, resistors 13, 14, 15, 16, 17, 18,
It is composed of three parts, that is, a single-ended differential conversion circuit composed of 19, 20 and a signal switching circuit composed of switches 21, 22, 23, 24, 25, 26.

The circuit operation will be described below in order from the input side. The switches 21 to 26 of the signal switching circuit are controlled by switching control signals S _{a to} S _f , respectively. S _a turns on the switch 21 in the odd-numbered rising section of the input signal. S
_{For c} , the switch 23 is turned on in the odd-numbered falling section and the even-numbered rising section of the input signal. S _e turns on the switch 25 in the even-numbered falling sections. Remaining S _b, S
_{d and} S _f operate one cycle behind S _a, S _{c and} S _e . That is, S _b turns on the switch 22 in the even-numbered rising sections of the input signal. S _d turns on the switch 24 in the even-numbered falling section and the odd-numbered rising section of the input signal. S _f turns on the switch 26 in the odd-numbered falling section. Therefore, the output V _a of the signal switching circuit is the same as the input signal in the odd-numbered rising sections of the input signal, and V _B in the odd-numbered falling sections and the even-numbered rising sections.
And the same voltage as V _BN in the even-numbered falling sections. Similarly, the output V _b of the signal switching circuit has the same voltage as the input signal in the even-numbered rising sections of the input signal, and the same voltage as V _B in the even-numbered falling sections and the odd-numbered rising sections, and the odd-numbered rising sections. In the falling section, the voltage is the same as V _BN .

Next, in the single-ended differential conversion circuit, V
The subtraction of _a and _Vb is performed. Generally, the input / output characteristics of this circuit are V _c = (V _b −V _a ), V _d = −, assuming that the outputs are V _{c and} V _d and the resistors 13 to 20 are all equal.
It can be represented by (V _b −V _a ). V _c and V _d are V
_The signal has a polarity opposite to that of _b .

In the next voltage dividing circuit, the output of the single-ended differential conversion circuit is divided. The reason for voltage division is that the linear operation range of the MOS transistors 1 and 2 is narrow. At the same time, the voltage dividing circuit produces the gate voltages of the MOS transistors 1 and 2. As described above, the gate voltage needs to be a signal similar to the input signal centered on the potential of V _G.

Drain voltage V of MOS transistor 1_in
⁺And the drain voltage V of the MOS transistor 2_in ^-Is
The resistance values of anti-7, 8, 11, 12 are R respectively.₇, R₈,
R₁₁, R ₁₂As V_in ⁺= V_c・ R₈/ (R₇+ R₈)… (6) V_in ^-= V_d・ R₁₂/ (R₁₁+ R₁₂) (7) Gate voltage V of MOS transistor 1_fAnd MOS transistor
Gate voltage V of transistor 2_eIs the resistance of resistors 5, 6, 9, 10
R is the resistance value_Five, R₆, R₉, R_TenThen, V_e= V_dd・ R₆/ (R_Five+ R₆) + V_C・ R_Five/ (R_Five+ R₆)… (8) V_f= V_dd・ R_Ten/ (R₉+ R_Ten) + V_d・ R₉/ (R₉+ R_Ten)… (9) R_Five= R₉, R₆= R_TenThen, equations (8) and (9)
As you can see, V _e, V_fIs a constant voltage V_dd・ R₆/
(R_Five+ R₆) = V_GCentered on_c, V_dMinutes
The pressed signal is output.

In the equation (5), α is the input signal also represented by the equation (6),
Considering that the voltage is divided by the equation (7), R ₇ = R
_{11, when} R ₈ = R ₁₂ α = R ₉ · R ₁₂ / (R ₉ + R ₁₀ ) · (R ₁₁ + R ₁₂ ) ... (10) V _{in in the} equation (5) is V only in the rising section of the input. _in · R ₈ / (R ₇ + R ₈ ) = V _in ⁺ V _in ⁻ (11), and the squared waveform of the input is obtained at the output from the equation (5). V _c, V _d, V _e, V for the input falling section
_{Since f} is clamped to the peak value by the switches 21 to 26 described above, the output value is also clamped to the peak value.

As described above, the circuit of FIG. 3 outputs the squared waveform only in the rising section of the input, and in the falling section of the input having a short time, the output is a constant value and does not output the squared waveform. In a CRT distortion correction waveform generation circuit for a television or the like, since the falling section is a section called a retrace section where an image cannot be seen on the screen, the squared waveform is originally unnecessary and the falling section is squared. When the waveform is output, it is necessary to amplify the frequency characteristic of the amplifier circuit connected in the subsequent stage to a relatively high frequency so that the influence does not affect the square waveform of the rising section.

When the circuit of FIG. 3 is applied to the distortion correction waveform generating circuit of the CRT, the frequency characteristic of the amplifier circuit connected in the subsequent stage may be one that amplifies a relatively low frequency.

[0020]

As described above, according to the present invention, M
A CRT distortion correction waveform generation circuit can be realized using OS transistors. Further, since the switch can also be easily realized and changed by a MOS transistor, when applied to a MOS type integrated circuit, the distortion correction waveform generating circuit of the CRT can be configured without adding an external capacitor switching function or the like. There is.

Further, since the output in the blanking interval can be clamped to a constant value and an unnecessary high frequency waveform is not output, there is an effect that the frequency characteristic of the circuit connected in the subsequent stage can be relaxed.

[Brief description of drawings]

FIG. 1 shows a first embodiment of the present invention.

FIG. 2 shows operation waveforms of various parts of the circuit of FIG.

FIG. 3 shows a second embodiment of the present invention.

FIG. 4 shows operation waveforms of various parts of the circuit of FIG.

[Explanation of symbols]

 1, 2, 3 MOS transistor 4 operational amplifier 5-20 resistor 21-26 switch

Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H04N 3/23 Z 7337-5C // G06F 101: 18

Claims (2)

[Claims] 1. A first MOS transistor having a drain connected to a first input terminal, a second MOS transistor having a drain connected to a second input terminal, and the first M transistor.
The inverting input terminal is connected to the source of the OS transistor and the source of the second MOS transistor in common, and the operational amplifier is connected to the non-inverting input terminal of the reference voltage, and the first terminal is connected to the inverting input terminal. , A resistance element in which a second terminal is connected to the output terminal of the operational amplifier,
A function generating circuit, wherein the gate of the first MOS transistor is connected to a third input terminal and the gate of the second MOS transistor is connected to a fourth input terminal. 2. A first input terminal for inputting a signal, a second input terminal for inputting a first reference voltage, a third input terminal for inputting a second reference voltage, and a third reference voltage. A fourth input terminal for inputting, and first, second, third, fourth, fifth, sixth switching of signals input to the input terminal group in sequence.
Switch, first and second differential amplifiers for inputting a signal selected by the switch, and the first and second differential amplifiers.
The first, the second, the third, and the fourth output terminals are attached to the two voltage dividers composed of the first and the second resistance groups, respectively, to which the outputs of the differential amplifier of A first MOS transistor having a drain connected, a second MOS transistor having a drain connected to the fourth output terminal, a source of the first MOS transistor, and the second MOS transistor.
Of the operational amplifier, the source of the MOS transistor is connected in common and the inverting input terminal is connected, and the fourth reference voltage is connected to the non-inverting input terminal, and the inverting input terminal is connected to the first terminal. A resistor element having a second terminal connected to the output terminal, the gate of the first MOS transistor is connected to the third output terminal, and the gate of the second MOS transistor is the first output. A function generating circuit characterized by being connected to a terminal.