JPS58102579A - Josephson integrated circuit - Google Patents

Josephson integrated circuit

Info

Publication number
JPS58102579A
JPS58102579A JP56201243A JP20124381A JPS58102579A JP S58102579 A JPS58102579 A JP S58102579A JP 56201243 A JP56201243 A JP 56201243A JP 20124381 A JP20124381 A JP 20124381A JP S58102579 A JPS58102579 A JP S58102579A
Authority
JP
Japan
Prior art keywords
electrode
integrated circuit
ground plane
window
base part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56201243A
Other languages
Japanese (ja)
Other versions
JPH0136274B2 (en
Inventor
Hideo Suzuki
秀雄 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56201243A priority Critical patent/JPS58102579A/en
Publication of JPS58102579A publication Critical patent/JPS58102579A/en
Publication of JPH0136274B2 publication Critical patent/JPH0136274B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/10Junction-based devices
    • H10N60/12Josephson-effect devices

Abstract

PURPOSE:To obtain the high degree of integration, by providing a window part in a ground plane, connecting a base part electrode and an opposing electrode on the window, thereby eliminating the slant in the threshold characteristic of a circuit and reducing the area of the connecting part. CONSTITUTION:The Josephson integrated circuit is composed of base part electrodes 21 and 21' wherein a bias current Ib flows, a load resistor 22, the opposing electrode 23 and 23', control electrodes 24 and 24' to which an input signal S is inputted, the base part electrode 25, the ground plane 26, and the window part 27 in the groun plane. In this integrated circuit, the ground plane is provided on the entire surface except the window part 27 under the connecting part of the opposing electrode 23 and the base part electrode 25. J1 and J2 indicate the Josephson junctions.

Description

【発明の詳細な説明】 (1)  発明の技術分野 本発明はジ曹セフノン接合を有するジ−セフノン集積回
路に関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a di-Cefnon integrated circuit having a di-Cefnon junction.

(コ 技術の背景 通常ジ曹セ7ソン接合を形成している対向電極は、基部
電極、制御電極と異なる材料を用いており(たとえば基
部電極と制御電極は鉛、インジ島りム、金の合金に対し
て、対向電極は鉛、ビスマスの合金!ある。)−例とし
て対向電極と、制御電極を接続した場合には、グレーン
マイグレーシ習ンが生じたり、対向電極の材料的な問題
から接触抵抗が生じたりする。これを避けるためにスイ
ッチ票子として使用しているジ璽セフンン接合に比べて
十分広い面積で対向′#IL4jから基部電極に接続し
たのち基部電極と制御電極とを接続する。
(Technical background) The counter electrode that forms the junction usually uses a different material from the base electrode and the control electrode (for example, the base electrode and the control electrode are made of lead, indium oxide, or gold). For example, when the counter electrode and control electrode are connected, grain migration may occur, or contact may occur due to problems with the material of the counter electrode. In order to avoid this, the base electrode and the control electrode are connected after connecting the opposite `#IL4j to the base electrode in a sufficiently wider area than the diagonal junction used as the switch tab.

(3)従来技術の問題点 この際従来は配線のインダクタンスを小さくしたり、ス
トリップライン構成のためのグランドプレーンがこの接
続部にも敷かれていた。
(3) Problems with the Prior Art At this time, in the past, the inductance of the wiring was reduced, and a ground plane for the strip line configuration was also laid at this connection portion.

例えば第1図(a) K示すインライン屋のジ璽七7ソ
ン接合で対向電極1と基部電極2が接続され、グランド
プレーン3がその接続部の下にも設けられていると、グ
ランドプレーン3に流れるイメージ電流によりその閾値
は第1図(ロ)に示すようKなる。
For example, if the counter electrode 1 and the base electrode 2 are connected by the in-line junction shown in FIG. The threshold value becomes K as shown in FIG. 1(b) due to the image current flowing in the image current.

即ち第111(b)において外部磁界φと臨界電流Ic
の特性は外部磁界が無い状態で最大の臨界電#lKなら
ない、従ってこれを防止するためkは接続部の面積を大
きくしなければならず、高集積化のさまたげとなってい
た (6)発明の目的 本発明の目的は、しきい値特性の傾斜をなくし接続部の
面積を小さくするととにある。
That is, in No. 111(b), the external magnetic field φ and the critical current Ic
The characteristic of this is that the maximum critical voltage #lK cannot be achieved in the absence of an external magnetic field. Therefore, in order to prevent this, the area of the connection part must be increased for k, which hinders high integration (6) Invention OBJECTS OF THE INVENTION An object of the present invention is to eliminate the slope of the threshold characteristic and reduce the area of the connection portion.

(5)発明の構成 上記目的は、グランドプレーン上に基部電極および対向
電極を有するジ曹セ7ソン集積回路において、該グラン
ドプレーンに窓部が設けられ、皺窓部上で該基部電極と
鋏対向電極とが接続されることkより達成される。
(5) Structure of the Invention The above object is to provide a semiconductor integrated circuit having a base electrode and a counter electrode on a ground plane, in which a window is provided in the ground plane, and the base electrode and scissors are connected to each other on the wrinkled window. This is achieved by connecting the opposing electrodes.

(@ 発明のlI!施例 第2図は本発明の一実施例を説明する図で、第211(
a)は平Wi図、第21i1(b)はその等価回路図で
ある。
(@ lI! Example of the invention Figure 2 is a diagram explaining an example of the present invention, and No. 211 (
21i1(b) is its equivalent circuit diagram.

第21Ia(a)K*イテ21 、21 ’ ハ/((
アx電流rbが流れる基部電極、22は負荷抵抗、23
.23’は対向電極、24.24’は入力信号Sが入力
される制御電極、25は基部電極、26はグランドプレ
ーン、27はグランドプレーンKlI&けられた窓部で
ある。
21st Ia(a) K*ite 21, 21' Ha/((
A base electrode through which the ax current rb flows, 22 is a load resistance, 23
.. 23' is a counter electrode, 24 and 24' are control electrodes to which the input signal S is input, 25 is a base electrode, 26 is a ground plane, and 27 is a ground plane KlI & cut window.

グランドプレーン26は、対向電極23と基部電極25
の接続部の下の窓部27を除いて一面に設けられている
The ground plane 26 has a counter electrode 23 and a base electrode 25.
It is provided on one side except for the window section 27 below the connection section.

第2図伽)の等節回路に明らかな通り、本実施例は入力
信号を次段へ伝達するための回路である。
As is clear from the equinodal circuit shown in FIG. 2, this embodiment is a circuit for transmitting an input signal to the next stage.

図中のJl、Jtはジ■七フソン接合を示す。Jl and Jt in the figure indicate di-7fson junctions.

(n 発明の効果 本発明によれば、ジ冒セフソン集積回路における基部電
極と対向電極の接続部面積を小さく出来るのでジ1七フ
ソン接合による集積回路の集積度を高める事が出来る。
(n) Effects of the Invention According to the present invention, since the area of the connecting portion between the base electrode and the counter electrode in the diopter integrated circuit can be reduced, the degree of integration of the integrated circuit using the diopter junction can be increased.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例を説明する図、第2図は、本発明の−!
#!麹例を説明する図である。21.21’。 25:基部電極、23.23’:対向電極、26:グラ
ンドプレーン、27:窓部。 褐 1 口 #52 図
FIG. 1 is a diagram explaining the conventional example, and FIG. 2 is a diagram explaining the -! of the present invention.
#! It is a figure explaining an example of koji. 21.21'. 25: base electrode, 23.23': counter electrode, 26: ground plane, 27: window. Brown 1 Mouth #52 Diagram

Claims (1)

【特許請求の範囲】[Claims] グランドプレーン上に基部電極および対向電極を有する
ジ−セフノン集積回路において、鋏グランドプレーンK
g部が設けられ、峡窓部上で該基部電極と鋏対向電極と
が接続されてなることを特徴とするジ−セフノン集積回
路。
In a G-CEFN integrated circuit having a base electrode and a counter electrode on the ground plane, the scissors ground plane K
1. A G-Cefnon integrated circuit, characterized in that a g section is provided, and the base electrode and the scissors counter electrode are connected on the isthmus window section.
JP56201243A 1981-12-14 1981-12-14 Josephson integrated circuit Granted JPS58102579A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56201243A JPS58102579A (en) 1981-12-14 1981-12-14 Josephson integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56201243A JPS58102579A (en) 1981-12-14 1981-12-14 Josephson integrated circuit

Publications (2)

Publication Number Publication Date
JPS58102579A true JPS58102579A (en) 1983-06-18
JPH0136274B2 JPH0136274B2 (en) 1989-07-31

Family

ID=16437706

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56201243A Granted JPS58102579A (en) 1981-12-14 1981-12-14 Josephson integrated circuit

Country Status (1)

Country Link
JP (1) JPS58102579A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60178675A (en) * 1984-02-24 1985-09-12 Agency Of Ind Science & Technol Superconductive transformer
JP2007112548A (en) * 2005-10-19 2007-05-10 Gecoss Corp Steel sheet pile lifting tool

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60178675A (en) * 1984-02-24 1985-09-12 Agency Of Ind Science & Technol Superconductive transformer
JPH0231512B2 (en) * 1984-02-24 1990-07-13 Kogyo Gijutsuin
JP2007112548A (en) * 2005-10-19 2007-05-10 Gecoss Corp Steel sheet pile lifting tool

Also Published As

Publication number Publication date
JPH0136274B2 (en) 1989-07-31

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