JPH0411125B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor relay circuit, and more particularly to a semiconductor relay circuit that utilizes isolation by optical coupling.

(Background Art) Conventionally, semiconductor relay circuits that combine a photocoupler and a MOSFET have been proposed. In this conventional example, for example, the input terminal of the relay
An LED is connected, the light from this LED is received by a photodiode array, and the voltage generated across the photodiode array is applied between the gate and source of the MOSFET, and a relay is applied between the source and drain of the MOSFET. It was used as an output terminal.

However, in order to achieve high-speed switching characteristics in this type of semiconductor relay circuit, when an optical signal is output, the switching element must be controlled by an electrical signal generated in the light receiving element that receives the optical signal. In addition to quickly increasing the terminal voltage, when the optical signal is interrupted, it is necessary to quickly discharge the charge accumulated in the control terminal of the switching element and quickly lower the control terminal voltage. For this reason, various control circuits have been added to this type of semiconductor relay circuit to achieve the above operations, but the circuit configuration has become complicated and expensive, or conversely, the circuit configuration has been too simple. There were many cases where we could not expect sufficient effects.

Therefore, the present inventors recognized that a necessary condition for a control circuit is to quickly charge and discharge the charge accumulated in the control terminal of the element that switches between the output terminals of the relay. As a result of examining various elements suitable as components of such control circuits, and after much trial and error, we decided on the recently developed insulated gate planar thyristor (IGT).
We have found that a gate planar thyristor (Gate Planar Thyristor) is an extremely effective device.

(Object of the Invention) The present invention has been made based on the above-mentioned knowledge, and its purpose is to provide a control circuit for quickly charging and discharging the control voltage of a switching element, and to provide a high-speed switching device. The object of this invention is to realize a semiconductor relay circuit that enables switching with a simple circuit configuration using an insulated gate planar thyristor.

(Disclosure of the Invention) Basic Configuration FIG. 1 is a circuit diagram showing the basic configuration of the present invention. In the semiconductor relay circuit according to the present invention,
As shown in FIG. 1, a pair of input terminals 1
0 and 11, a light emitting element 1 connected to the input terminals 10 and 11, a light receiving element 2 that receives an optical signal from the light emitting element 1 and outputs an electrical signal, and a light receiving element 2 connected between both ends of the light receiving element 2. a first resistor 4 and a diode 3 whose anode is connected to the anode of the light receiving element 2.
and a first P-channel MOSFET 5 whose source and N-type substrate are connected to the cathode of the diode 3 and whose gate is connected to the anode of the diode 3;
An anode terminal is connected to the cathode of the diode 3, a cathode terminal is connected to the cathode of the light receiving element 2, and a gate terminal is connected to the first P channel.
An insulated gate planar thyristor 6 is connected to the drain of the MOSFET 5, a source terminal is connected to the anode of the diode 3, a gate terminal is connected to the cathode of the light receiving element 2, and a drain element is connected to the N of the insulated gate planar thyristor 6. type semiconductor bulk layer, and the N type substrate is connected to the diode 3.
a second P-channel connected to the cathode of
A control terminal is connected between the MOSFET 7, a second resistor 8 connected between the gate terminal and the cathode terminal of the insulated gate planar thyristor 6, and the cathode of the diode 3 and the cathode of the light receiving element 2, It includes a switching element 9 whose impedance between current-carrying terminals changes depending on the voltage applied between the control terminals, and a pair of output terminals 12 and 13 connected to the current-carrying terminals of the switching element 9. Note that the gate of the second P-channel MOSFET 7 only needs to be substantially connected to the cathode of the light-receiving element 2, and the gate of the P-channel MOSFET 7 is connected to the gate of the insulated gate planar thyristor 6 through the resistor 8. P channel MOSFET
The gate of 7 may be connected to the cathode of the light receiving element 2.

Insulated gate planar thyristor 6 (hereinafter simply referred to as
Regarding the structure and basic operation of IGT6),
For example, IEEE TRANSACTIONS ON
ELECTRON DEVICES VOL.ED−27, No.2,
FEBRUARY 1980, etc., but I will briefly explain it here. The IGT 6 has a structure as shown in FIG. 2, and its equivalent circuit is shown in FIG. 3. In Figures 2 and 3, A
is an anode terminal, K is a cathode terminal, G is a gate terminal, and B is an N-type semiconductor bulk terminal. As shown in FIG. 2, one side of the N-type semiconductor bulk is heavily doped with P-type, and an anode terminal A is connected to this P-type region. In addition, on the other side of the N-type semiconductor bulk, a pair of weakly doped P-type regions are formed, the center of which is strongly doped with P-type, and a region strongly doped with P-type and a region weakly doped with P-type. The portion extending over the doped region is strongly doped with N type, and an aluminum electrode is deposited on this region which is heavily doped with N type to form a cathode terminal K. A gate electrode is arranged on the surface of the portion extending between the weakly P-doped region and the N-type semiconductor bulk via a thin insulating layer, and this gate electrode is connected to a gate terminal K. Further, a part of the N-type semiconductor bulk is strongly doped with N-type, an aluminum electrode is deposited thereon, and a bulk terminal B is connected to the N-type semiconductor bulk.

The equivalent circuit of the structure shown in FIG.
As shown in the figure, a PNP transistor and
The circuit consists of an NPN transistor connected in a thyristor structure, and an N-channel MOSFET connected in parallel between both ends of the NPN transistor.
That is, the base and collector of the PNP transistor are connected to the collector and base of the NPN transistor, respectively, the emitter of the PNP transistor is connected to the anode terminal A of IGT6, and the emitter of the NPN transistor is connected to the cathode terminal K of IGT6. be done. The collector and emitter of the NPN transistor are connected to the drain and source of the N-channel MOSFET, respectively. The source of the N-channel MOSFET is shared with the substrate terminal, and the gate is connected to the gate terminal G of the IGT6. Furthermore, the collector of the NPN transistor is connected to bulk terminal B.

Operation First, the operation of IGT6 will be explained. When a voltage is applied so that the anode terminal A has a positive potential with respect to the cathode terminal K, is the gate terminal G at the same potential as the cathode terminal K, and the bulk terminal B at the same potential as the anode terminal A? Or when the potential is higher than that of the anode terminal A,
N-channel MOSFET does not conduct, and PNP
Since the transistor is also in a zero bias or reverse bias state, it does not conduct, so no base current flows through the NPN transistor. Therefore, the anode and cathode of the IGT 6 are in a non-conducting state. Next, either the bulk terminal B becomes a lower potential than the anode terminal A, or the gate terminal G becomes a positive voltage level higher than a predetermined threshold voltage V _TH1 with respect to the cathode terminal K, and the N-channel MOSFET becomes conductive. When this happens, a current flows between the emitter and base of the PNP transistor in IGT6. As a result, when the PNP transistor becomes conductive, a base current flows through the NPN transistor, and the NPN transistor also becomes conductive. When the NPN transistor becomes conductive, a current path through the base of the PNP transistor is secured, and the anode and cathode of the IGT 6 become conductive due to the thyristor phenomenon. In this way, compared to a normal thyristor, the IGT6 has a bulk terminal B, and if this bulk terminal B is pulled up to a higher potential than the anode terminal A, the thyristor can be prevented from being turned on inadvertently. It is now possible to definitely prevent this.

Next, the overall operation of the circuit shown in FIG. 1 will be explained.

In the circuit shown in FIG. 1, when a voltage is applied between input terminals 10 and 11 by an external circuit, light emitting element 1 outputs an optical signal. The light receiving element 2 receives this optical signal, generates an electric signal, and generates a voltage signal across the resistor 4. This voltage signal is passed through the anode and cathode of the diode 3 to the switching element 9.
is applied to the control terminal of At this time, since the diode 3 is biased in the forward direction, the gate and source of the P-channel MOSFET 5 are reverse biased, and the P-channel MOSFET 5 is not conductive. Therefore, the gate terminal G of the IGT 6 is at the same potential as the cathode terminal K. Also,
P-channel MOSFET 7 is in a conductive state,
Since a positive charge is poured into the bulk terminal B of the IGT 6, the IGT 6 is prevented from causing a thyristor phenomenon and becoming conductive. Therefore, there is a high impedance between the control terminals of the switching element 9, and the voltage at the control terminal of the switching element rapidly increases due to the output from the light receiving element 2.
As a result, the impedance state between the current-carrying terminals of the switching element 9 is either high impedance or low impedance.

Next, when the voltage between the input terminals 10 and 11 is removed and the optical signal from the light emitting element 1 is cut off, the generation of the electrical signal by the light receiving element 2 is stopped. At this time, the charge in the light receiving element 2 is discharged through the resistor 4, and the voltage across the light receiving element 2 rapidly decreases. On the other hand, the charge accumulated in the control terminal of the switching element 9 is prevented from flowing backward by the diode 3, so that it is not discharged through the path via the diode 3. Therefore, P channel
The source potential of MOSFET 5 becomes higher than the gate potential, and the source-drain impedance of P-channel MOSFET 5 decreases. As a result, the voltage V ₁ across the resistor 8 increases, and the voltage at the gate terminal G of the IGT 6 increases. The voltage V ₁ is
When the voltage becomes higher than the threshold voltage V _TH1 of the N-channel MOSFET in the IGT 6, conduction occurs between the anode and cathode of the IGT 6. Therefore, the charge accumulated in the control terminal of the switching element 9 is rapidly discharged, and the impedance state between the current-carrying terminals of the switching element 9 becomes either high impedance or low impedance.

Embodiment 1 Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 4 is a circuit diagram of an embodiment of the present invention. In this embodiment, an enhancement type MOSFET 9 is used as the switching element 9. Figure 5 shows the diagram used in this example.
The relationship between the drain current I _D of MOSFET 9a and the gate-source voltage V _GS is shown. In the example circuit, the anode of the light receiving element 2 is connected to the anode through the diode 3.
It is connected to the gate terminal G of MOSFET 9a, and its cathode is connected to the source terminal S of MOSFET 9a. In addition, in the MOSFET 9a, the drain terminal D is used as the output terminal 12 of the relay, and the source terminal S is used as the output terminal 13 of the relay, and when the MOSFET 9a is in the off state, the output terminal 12 is at a positive potential with respect to the output terminal 13. It is used in a maintained state, and operates to flow current from one output terminal 12 to the other output terminal 13 when it is in the on state. Furthermore, the substrate of the MOSFET 9a is connected to the source terminal S. The other configurations are the same as the basic configuration shown in FIG.

The operation of this embodiment will be explained below. When a voltage of the illustrated polarity is applied between the input terminals 10 and 11, an optical signal is generated from the light emitting element 1 made of an LED. The light-receiving element 2 made of a photodiode array generates an electrical signal when it receives the optical signal, and applies a voltage V _S approximately determined by the product of the short-circuit current and the value of the first resistor 4 to the light-receiving element. 2
A positive potential is generated at both ends of the anode so that the anode side has a more positive potential than the cathode side. The anode of the light receiving element 2 is connected to the gate of the MOSFET 9a through the diode 3, and the cathode is connected to the source of the MOSFET 9a. Therefore, between the gate and source of the MOSFET 9a, the gate terminal is at a positive potential with respect to the source terminal, and the potential difference is is from the voltage V _S to diode 3
The gate terminal is charged until it becomes equal to the voltage value minus the conduction voltage of . When this voltage V _S exceeds the threshold voltage V _TH of MOSFET 9a in the positive direction, MOSFET 9a becomes conductive according to the characteristics shown in FIG. A current flows towards.

At this time, the source voltage of the P-channel MOSFET 5 is kept lower than the gate voltage by the forward voltage drop of the diode 3, so it is in a non-conductive state and does not affect the charging operation of the gate terminal of the MOSFET 9a. Also, this P channel
Since the MOSFET 5 is in a non-conductive state, no potential difference is generated between both ends of the resistor 8, and therefore no voltage is generated at the gate terminal G of the IGT 6. For this reason, IGT
6 is a non-conducting state. Also, P channel
The MOSFET 7 is in a conductive state and a positive charge is poured into the bulk terminal B of the IGT 6, thereby preventing the IGT 6 from causing a thyristor phenomenon and becoming conductive. In this way, each element connected between the gate and source of MOSFET 9a is connected to the light receiving element 2.
The charges generated by the gate are not discharged during the period when the optical signal is present, and are
Does not affect charging operation between sources.

When the input signal to the light emitting element 1 made of an LED is made zero and the optical signal is cut off, first, the voltage V _S generated across the first resistor 4 becomes zero.
Since positive charges are accumulated in the gate terminal of the MOSFET 9a, the anode and cathode of the diode 3 are in a reverse bias state. For this reason, MOSFET9
The positive charge accumulated on the gate of a diode 3
, and is not discharged via the diode 3. Further, as the voltage V _S becomes zero, the gate voltage of the P-channel MOSFET 5 also becomes zero, and the P-channel MOSFET 5 becomes conductive.
The positive charge accumulated in the gate of MOSFET 9a is discharged through the P-channel MOSFET 5 and second resistor 8. This generates a voltage V ₁ across the second resistor 8 . The second resistor 8 is connected so that this voltage V ₁ exceeds the threshold voltage V _TH1 of the N-channel MOSFET in the IGT 6 shown in FIG.
If the resistance value is set, when the voltage V ₁ exceeds the threshold voltage V _TH1 , the N-channel MOSFET in IGT6 becomes conductive, and from the anode terminal of IGT6 to the cathode terminal, MOSFET9a
The positive charge accumulated in the gate of flows. This charge flow becomes a trigger current, causing the thyristor phenomenon of IGT6, and the gate of MOSFET9a.
Rapidly discharges the positive charge accumulated between the sources. If the absolute value of V _TH of MOSFET 9a is set to be higher than the forward voltage drop V _C during conduction that causes the thyristor phenomenon of IGT 6, MOSFET 9
As the charge at the gate terminal is discharged, a quickly becomes non-conductive, and the relay also turns off. In this example, the enhancement type
Immediately charge the gate terminal of MOSFET9a,
In addition, since the accumulated charge can be rapidly discharged, it is possible to realize a normally-open type (normally-off type) semiconductor relay circuit in which the relay can be turned on and off at high speed.

Embodiment 2 FIG. 6 is a circuit diagram of another embodiment of the present invention.
In this embodiment, a depletion type MOSFET 9b is used as the switching element 9. Figure 7 shows the diagram used in this example.
The relationship between the drain current _ID of MOSFET 9b and the gate-source voltage V _GS is shown. In the example circuit, the drain terminal D of the MOSFET 9b is used as the output terminal 13 of the relay, and the source terminal S is used as the output terminal 12 of the relay, so that the output terminal 13 is connected to the output terminal 12 when in the off state. It is used while being kept at a positive potential, and when it is in the on state, one output terminal 13 is connected to the other output terminal 1.
It operates in such a way that current flows toward 2. Furthermore, the substrate of MOSFET 9b is connected to the source terminal. The other configurations are the same as the basic configuration shown in FIG.

The operation of this embodiment will be explained below. When a voltage of the illustrated polarity is applied between the input terminals 10 and 11, an optical signal is generated from the light emitting element 1 made of an LED. The light-receiving element 2 made of a photodiode array generates an electrical signal when it receives the optical signal, and applies a voltage V _S approximately determined by the product of the short-circuit current and the value of the first resistor 4 to the light-receiving element. 2
A positive potential is generated at both ends of the anode so that the anode side has a more positive potential than the cathode side. The anode of the light receiving element 2 is connected to the source of the MOSFET 9b through the diode 3, and the cathode is connected to the gate of the MOSFET 9b. Therefore, between the gate and source of the MOSFET 9b, the gate terminal is at a negative potential with respect to the source terminal, and the potential difference is is from the voltage V _S to diode 3
The gate terminal is charged until it becomes equal to the voltage value minus the conduction voltage of . When this voltage V _S exceeds the threshold voltage V _TH of MOSFET 9b in the negative direction, MOSFET 9b is cut off according to the characteristics shown in FIG. The current going to is cut off.

At this time, the source voltage of the P-channel MOSFET 5 is kept lower than the gate voltage by the forward voltage drop of the diode 3, so it is in a non-conductive state and does not affect the charging operation of the gate terminal of the MOSFET 9b. Also, this P channel
Since the MOSFET 5 is in a non-conductive state, no potential difference is generated between both ends of the resistor 8, and therefore no voltage is generated at the gate terminal G of the IGT 6. For this reason, IGT
6 is a non-conducting state. Also, P channel
The MOSFET 7 is in a conductive state and a positive charge is poured into the bulk terminal B of the IGT 6, thereby preventing the IGT 6 from causing a thyristor phenomenon and becoming conductive. In this way, each element connected between the gate and source of MOSFET 9b is connected to the light receiving element 2.
The charges generated by the gate are not discharged during the period when the optical signal is present, and are
Does not affect charging operation between sources.

When the input signal to the light emitting element 1 made of an LED is made zero and the optical signal is cut off, first, the voltage V _S generated across the first resistor 4 becomes zero.
Since negative charges are accumulated in the gate terminal of MOSFET 9b, the anode and cathode of diode 3 are in a reverse bias state. For this reason, MOSFET9
The negative charge accumulated on the gate of diode 3
, and is not discharged via the diode 3. Further, as the voltage V _S becomes zero, the gate voltage of the P-channel MOSFET 5 also becomes zero, and the P-channel MOSFET 5 becomes conductive.
The negative charges accumulated in the gate of MOSFET 9b are discharged through the P-channel MOSFET 5 and the second resistor 8. This generates a voltage V ₁ across the second resistor 8 . The second resistor 8 is connected so that this voltage V ₁ exceeds the threshold voltage V _TH1 of the N-channel MOSFET in the IGT 6 shown in FIG.
By setting _a resistance value _of
Negative charges accumulated in the gate of the circuit flow. This charge flow becomes a trigger current, causing a thyristor phenomenon in the IGT 6, and rapidly discharging the negative charge accumulated in the gate terminal of the MOSFET 9b.
If the absolute value of V _TH of MOSFET9b is set to be higher than the forward voltage drop V _C during conduction that causes the thyristor phenomenon of IGT6, MOSFET9b will rapidly become conductive as the charge at the gate terminal is discharged, and the relay will is also turned on. In this example, the depletion type MOSFET is
Since the gate terminal 9b can be quickly charged and the accumulated charge can be rapidly discharged, it is possible to realize a normally-on type semiconductor relay circuit that can turn on and off the relay at high speed. It is possible.

In each of the above embodiments, only the case where a DC relay is configured has been described, but it is also possible to configure an AC relay. For example, the switching element 9 may be a gate of a pair of MOSFETs.
By connecting the sources in common, making this the control terminal of the switching element 9, and making the drain of each MOSFET the current-carrying terminal, it is possible to realize a relay that switches alternating current.

(Effects of the Invention) As described above, in the present invention, the insulated gate planar thyristor is connected between the control terminals of the switching element, so that once the thyristor is turned on, the self-holding action prevents the switching element from being controlled. A first P-channel for providing a trigger voltage to the gate terminal of the thyristor, which allows the charge between the terminals to be almost completely discharged, thus allowing a rapid discharge of the accumulated charge;
A diode is connected between the gate and source of the MOSFET, and when an electrical signal is generated in the light receiving element by an optical signal from the light emitting element, the first P
Since the channel MOSFET is reverse biased, the thyristor will not conduct, and
In this state, the second P channel
Since the bulk terminal of the thyristor is pulled up to a positive voltage by the MOSFET, the thyristor is not turned on inadvertently, and the control terminal of the switching element is reliably set to high impedance and the control terminal is quickly charged. Therefore, there is an effect that extremely high-speed switching can be realized with a simple configuration.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing the basic configuration of the present invention, Figure 2 is a circuit diagram showing the basic configuration of the present invention.
The figure is an explanatory diagram showing the cross-sectional structure of the insulated gate planar thyristor used in the same as above, FIG. 3 is a circuit diagram showing an equivalent circuit in the same as above, FIG. FIG. 6 is a characteristic diagram of the switching element used in the embodiment, FIG. 6 is a circuit diagram of another embodiment of the present invention, and FIG. 7 is a characteristic diagram of the switching element used in the above embodiment. 1 is a light emitting element, 2 is a light receiving element, 3 is a diode, 4 is a first resistor, 5 is a P channel
MOSFET, 6 is IGT, 7 is P channel
MOSFET, 8 is a second resistor, 9 is a switching element, 10 and 11 are input terminals, and 12 and 13 are output terminals.

Claims (1)

[Scope of Claims] 1. A pair of input terminals, a light emitting element connected to the input terminal, a light receiving element that receives an optical signal from the light emitting element and outputs an electrical signal, and a connection between both ends of the light receiving element. a first resistor, a diode whose anode is connected to the anode of the light receiving element, and a first P channel whose source and N-type substrate are connected to the cathode of the diode and whose gate is connected to the anode of the diode. MOSFET, an anode terminal connected to the cathode of the diode, a cathode terminal connected to the cathode of the light receiving element, and a gate terminal connected to the first
an insulated gate planar thyristor connected to the drain of the P-channel MOSFET, a source terminal connected to the anode of the diode, a gate terminal connected to the cathode of the light receiving element, and a drain terminal connected to the N-type insulated gate planar thyristor. a second P channel connected to the semiconductor bulk layer and with an N type substrate connected to the cathode of the diode;
A MOSFET, a second resistor connected between the gate terminal and the cathode terminal of the insulated gate planar thyristor, and a control terminal connected between the cathode of the diode and the cathode of the light receiving element, and a control terminal connected between the control terminals. A semiconductor relay circuit comprising: a switching element whose impedance between current-carrying terminals changes depending on an applied voltage; and a pair of output terminals connected to the current-carrying terminals of the switching element. 2. In the circuit described in claim 1,
The switching element is normally open, with low impedance between the current-carrying terminals when a voltage of a predetermined value or higher is applied between the control terminals, and high impedance between the current-carrying terminals when no voltage is applied between the control terminals. A semiconductor relay circuit characterized by being a type switching element. 3. In the circuit described in claim 1,
The switching element is normally closed, with high impedance between the current-carrying terminals when a voltage of a predetermined value or higher is applied between the control terminals, and low impedance between the current-carrying terminals when no voltage is applied between the control terminals. A semiconductor relay circuit characterized by being a type switching element.