JP2932782B2 - Semiconductor relay circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor relay circuit using an optical coupling system for isolation between input and output.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram of a conventional semiconductor relay circuit (Japanese Patent Application No. 1-166325). Hereinafter, the circuit configuration will be described. The light emitting diode 1 is connected between the relay input terminals I1 and I2. A photovoltaic diode array 2 is optically coupled to the light emitting diode 1. The positive electrode of the photovoltaic diode array 2 is connected via a resistor 3 to the gate of an NMOS-type enhancement mode output FET 4. The negative electrode of the photovoltaic diode array 2 is connected to the source of the output FET 4. The source and the drain of the control FET 5 in the depletion mode are connected to the gate and the source of the output FET 4, respectively. The gate of the control FET 5 is connected to the positive electrode of the photovoltaic diode array 2. The drain and source of the output FET 4 are connected to the relay output terminals O1 and O2, respectively. The base of the NPN transistor 6 is connected to the positive electrode of the photovoltaic diode array 2, the emitter is connected to the gate of the output FET 4, and the collector is connected to the drain of the output FET 4 via the rectifying element 7 for preventing backflow. doing.

A signal source S is connected as an external circuit via a resistor R between the relay input terminals I1 and I2. A load Z is connected as an external circuit between the relay output terminals O1 and O2.
And a series circuit of a DC power supply E are connected with the illustrated polarity. Now, when an input current flows from the signal source S to the light emitting diode 1 via the resistor R, the light emitting diode 1 generates an optical signal. Receiving this optical signal, the photovoltaic diode array 2 generates a current. This current flows to the resistor 3 through the source and drain of the control FET 5 which is always in a low impedance state. When the voltage generated by the resistor 3 exceeds the threshold voltage of the control FET 5, the control FET
5 is in a high impedance state. As a result, the current from the photovoltaic diode array 2 is output from the output FET 4
Charge between the gate and the source. Further, the voltage generated by the resistor 3 causes a forward bias between the base and the emitter of the transistor 6, and the collector and the emitter of the transistor 6 become conductive. Thereby, the load Z, the relay output terminal O1, the rectifying element 7 for preventing backflow,
A charging current flows between the gate and source of the output FET 4 via the collector and the emitter of the transistor 6. Therefore, the gate-source voltage of the output FET 4 increases quickly. When this voltage exceeds the threshold voltage of the output FET 4, the output FET 4 is turned on, and the relay output terminals O1 and O2 conduct. As a result, a load current flows from the DC power supply E to the load Z. Thereafter, a small current flows through the resistor 3 through the source and the drain of the control FET 5, and the bias voltage generated in the resistor 3 keeps the control FET 5 in a high impedance state. After the output FET 4 is completely turned on, the voltage between the drain and the source becomes almost zero.
Current flows from the drain to the source of the output FET 4 through the PN junction between the base and the collector of the transistor 6. , No current flows.

When the input current between the relay input terminals I1 and I2 is cut off and the light signal from the light emitting diode 1 is lost, the output current from the photovoltaic diode array 2 is lost. At this time, since the base and the emitter of the transistor 6 are reverse-biased by the gate-source voltage of the output FET 4, the collector and the emitter are non-conductive. Further, since the voltage between the gate and the source of the control FET 5 decreases due to the disappearance of the photoelectromotive force, the control FET 5 enters a low impedance state and the output FE
The charge stored in the gate-source capacitance of T4 is rapidly discharged through the control FET 5. As a result, the output FET 4 is turned off, and the connection between the relay output terminals O1 and O2 is cut off.

[0005]

In the prior art, a forward bias for making the transistor 6 conductive is obtained by using the resistor 3 for biasing the control FET 5 to a high impedance state. Therefore, the control FET 5
Is the base-emitter voltage (about 0.5 V) when the transistor 6 is turned on.
It cannot be set higher than V). Otherwise, the control FE
T5 cannot go into a high impedance state forever. Also, the threshold voltage Vt of the control FET 5
h is a current Id that can flow between the drain and source when the gate and source of the FET 5 are not biased.
There is a positive correlation with s. This current Ids is output FET
When 4 becomes non-conductive, it becomes a discharge current of the stored charge between its gate and source. Therefore, this current Ids
Is larger, the turn-off time of the output FET 4 can be shortened. However, as described above, in the conventional circuit, F
Since the threshold voltage of ET5 cannot be set higher than about 0.5 V, the current Ids cannot be increased beyond a certain value.

SUMMARY OF THE INVENTION The present invention has been made in view of the foregoing, and it is an object of the present invention to shorten the time required for increasing the gate-source voltage of an output FET and increase the speed of a semiconductor relay circuit. And providing a circuit configuration in which constants of circuit elements can be easily set.

[0007]

According to the first aspect of the present invention, in order to solve the above-mentioned problems, as shown in FIG.
Light emitting diode 1 that generates an optical signal in response to an input signal
When, that is positioned to receive light signals of the light-emitting diode 1 photovoltaic diode array 2, one end photovoltaic da
A first resistor 3 connected to an ion array 2;
Photovoltaic at the time of photovoltaic generation by the power diode array 2
Applied from the power diode array 2 to the gate and source.
Output that conducts between the drain and source due to the applied voltage
FET4 and one end connected to the gate of output FET4.
The second resistor 8 is connected in parallel between both ends of the second resistor 8.
Charge accumulated between the gate and source of the output FET 4
Diode connected with the direction of discharging
9 and a pair of control output terminals via the first resistor 3
When connected between both ends of the electromotive force diode array 2,
And the gate source of the output FET 4 via the second resistor 8.
And a control input terminal connected to the one end of the first resistor 3.
And a pair of control outputs when an optical signal is generated.
Light of the photovoltaic diode array 2 that is energized through the end
High resistance due to voltage generated in the first resistor 3 by current
And the output FET 4 when the optical signal is lost.
That constitute a discharge path for stored charge between the gate and
A first control transistor 5 of the normally-on type;
An emitter at one end of the second resistor 8 and the other end of the second resistor 8
Is connected to the base, and the collector is connected to the drain of the output FET4.
Consists of a bipolar transistor 6 connected to the in side
Drain of second control transistor and output FET 4
And the collector of the second control transistor.
And a diode 7 for preventing backflow . According to the invention of claim 2, FIG.
As shown in FIG.
That uses an element type MOSFET 16.
You.

[0008]

According to the present invention, when a charging current flows through the gate of the output FET 4, a low impedance state is established.
A transistor 6 for forming a charge path for the accumulated charge between the gate and the source of the output FET 4 or enhancement
Type MOSFET 16 is connected between the drain and gate of the output FET 4 via a rectifying element 7 for preventing backflow, and this circuit is used for controlling the formation of a discharge path for accumulated charges between the gate and source of the output FET 4 . FET5 with high resistance
Other than the resistor 3 for obtaining the voltage for controlling the
Since the on-state control is performed by the resistance 8 , setting of circuit constants is easier than in the past, and it is possible to obtain switching characteristics equivalent to or higher.

[0009]

FIG. 1 is a circuit diagram of an embodiment of the present invention. Hereinafter, the circuit configuration will be described. Relay input terminal I
The light emitting diode 1 is connected between 1 and I2.
A photovoltaic diode array 2 is optically coupled to the light emitting diode 1. The positive electrode of the photovoltaic diode array 2 is connected via a resistor 3 and a resistor 8 to the gate of an NMOS-type enhancement mode output FET 4. The negative electrode of the photovoltaic diode array 2 is connected to the source of the output FET 4. The control FET 5 in the depletion mode is connected to the gate of the output FET 4 via the anode and the cathode of the diode 9.
Sources are connected. The source of the output FET 4 is connected to the drain of the depletion mode control FET 5. The gate of the control FET 5 is connected to the positive electrode of the photovoltaic diode array 2. The drain and source of the output FET 4 are connected to the relay output terminals O1 and O2, respectively. Also, NPN
The base of the transistor 6 is connected to the connection point of the resistor 3 and the resistor 8, the emitter is connected to the gate of the output FET 4, and the collector is connected to the output FET via a rectifying element 7 for preventing backflow.
4 is connected to the drain.

A signal source S is connected as an external circuit between the relay input terminals I1 and I2 via a resistor R. A load Z is connected as an external circuit between the relay output terminals O1 and O2.
And a series circuit of a DC power supply E are connected with the illustrated polarity. Now, when an input current flows from the signal source S to the light emitting diode 1 via the resistor R, the light emitting diode 1 generates an optical signal. Receiving this optical signal, the photovoltaic diode array 2 generates a current. This current flows to the resistor 3 through the source and drain of the control FET 5 which is always in a low impedance state. When the voltage generated by the resistor 3 exceeds the threshold voltage of the control FET 5, the control FET
5 is in a high impedance state. As a result, the current from the photovoltaic diode array 2 is output from the output FET 4
Charge between the gate and the source. Also, a charging current flows between the gate and the source of the output FET 4 via the resistor 8, and a voltage is generated across the resistor 8. The voltage generated by the resistor 8 causes a forward bias between the base and the emitter of the transistor 6, and the collector and the emitter of the transistor 6 become conductive. Thereby, from the DC power source E, through the load Z, the relay output terminal O1, the rectifying element 7 for preventing reverse current, and the collector and emitter of the transistor 6,
A charging current flows between the gate and the source of the output FET 4. Therefore, the gate-source voltage of the output FET 4 increases quickly. When this voltage exceeds the threshold voltage of the output FET 4, the output FET 4 is turned on, and the relay output terminals O1 and O2 conduct. As a result, a load current flows from the DC power supply E to the load Z. Thereafter, a small current flows through the resistor 3 through the source and the drain of the control FET 5, and the bias voltage generated in the resistor 3 keeps the control FET 5 in a high impedance state. The output FET
After the transistor 4 is completely turned on, its drain-source voltage becomes almost zero, so that the current from the photovoltaic diode array 2 is output via the PN junction between the base and collector of the transistor 6. The current flows between the drain and source of the FET 4, but no current flows because the rectifying element 7 for preventing backflow is provided in this path.

When the input current between the relay input terminals I1 and I2 is cut off and the light signal from the light emitting diode 1 is lost, the output current from the photovoltaic diode array 2 is lost. At this time, since the base and the emitter of the transistor 6 are reverse-biased by the gate-source voltage of the output FET 4, the collector and the emitter are non-conductive. Further, since the voltage between the gate and the source of the control FET 5 decreases due to the disappearance of the photoelectromotive force, the control FET 5 enters a low impedance state and the output FE
The charge stored in the gate-source capacitance of T4 is rapidly discharged through the diode 9 and the control FET 5. As a result, the output FET 4 is turned off,
The connection between the relay output terminals O1 and O2 is cut off.

FIG. 2 is a circuit diagram of another embodiment of the present invention. In this embodiment, an enhancement-type MOSFET 16 is connected instead of the bipolar-type transistor 6. That is, the gate of the MOSFET 16 is connected to the resistor 3
To the positive electrode of the photovoltaic diode array 2 via
The source is connected to the gate of the output FET 4, and the drain is connected to the drain of the output FET 4 via the rectifying element 7 for preventing backflow. The operation is the same as in the embodiment of FIG. In this embodiment, the semiconductor relay
A circuit that accelerates turn-on and a circuit that accelerates turn-off
Can be formed individually, so the constants of the circuit elements can be set.
It becomes easy.

[0013]

According to the first aspect of the present invention, a circuit for accelerating turn-on of a semiconductor relay and a circuit for accelerating turn-off of a semiconductor relay can be separately formed. There is an effect that a possible semiconductor relay can be realized. Also, in the invention of claim 2,
A circuit that accelerates the turn-on of the semiconductor relay;
The circuit that accelerates the airflow can be formed separately
This has the effect of simplifying the setting of circuit element constants.
You.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention.

FIG. 2 is a circuit diagram of another embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 light emitting diode 2 photovoltaic diode array 3 resistor 4 output FET 5 control FET 6 transistor 7 rectifier 8 resistor 9 diode

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-88419 (JP, A) JP-A-2-292912 (JP, A) JP-A-5-191249 (JP, A) JP-A-4-192 324713 (JP, A) JP-A-4-20011 (JP, A) JP-A-3-297219 (JP, A) JP-A-3-96011 (JP, A) JP-A-2-244907 (JP, A) JP-A-2-20119 (JP, A) JP-A-2-7428 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H03K 17/00-17/98

Claims (2)

(57) [Claims] An optical signal is generated in response to an input signal.
A light emitting diode,  Light arranged to receive the light signal of the light emitting diode
An electromotive force diode array;A first resistor connected at one end to the photovoltaic diode array
Anti and Light generated when photovoltaic power is generated by the photovoltaic diode array
The voltage applied between the gate and the source from the electromotive force diode array
Voltage may cause conduction between the drain and source.
Power FET, A second resistor having one end connected to the gate of the output FET
When, It is connected in parallel between both ends of the second resistor, and the output FET
The direction in which the accumulated charge between the gate and source is discharged is the forward direction.
A diode connected as A pair of control output terminals are connected to the photovoltaic
A second resistor is connected between both ends of the ion array.
Connected between the gate and source of the output FET via a resistor
A control input terminal is connected to the one end of the first resistor;
When a signal is generated, power is supplied through the pair of control output terminals.
The first resistor due to the photocurrent of the photovoltaic diode array
It is biased to a high resistance state by the voltage generated by the
When the signal disappears, the charge between the gate and source of the output FET is stored.
A first normally-on type which constitutes a discharge path for accumulated charges
A control transistor; An emitter at one end of the second resistor, and another end at the other end of the second resistor;
Is connected to the base and the collector is the drain of the output FET.
A second bipolar transistor connected to the
A control transistor, The drain of the output FET and the second control transistor
A diode connected between the collectors to prevent backflow
Consist of A semiconductor relay circuit, characterized in that: 2. An optical signal is generated in response to an input signal.
A light emitting diode, Light arranged to receive the light signal of the light emitting diode
An electromotive force diode array; A first resistor connected at one end to the photovoltaic diode array
Anti and Light generated when photovoltaic power is generated by the photovoltaic diode array
The voltage applied between the gate and the source from the electromotive force diode array
Between the drain and source by the applied voltage Outgoing
Power FET, A second resistor having one end connected to the gate of the output FET
When, It is connected in parallel between both ends of the second resistor, and the output FET
The direction in which the accumulated charge between the gate and source is discharged is the forward direction.
A diode connected as A pair of control output terminals are connected to the photovoltaic
A second resistor is connected between both ends of the ion array.
Connected between the gate and source of the output FET via a resistor
A control input terminal is connected to the one end of the first resistor;
When a signal is generated, power is supplied through the pair of control output terminals.
The first resistor due to the photocurrent of the photovoltaic diode array
It is biased to a high resistance state by the voltage generated by the
When the signal disappears, the charge between the gate and source of the output FET is stored.
A first normally-on type which constitutes a discharge path for accumulated charges
A control transistor; A source at the one end of the second resistor and a source at the other end of the second resistor
The gate is connected and the drain is the drain of the output FET
From the enhancement-type MOSFET connected to the
A second control transistor, The drain of the output FET and the second control transistor
Such as a diode for blocking reverse current connected between the drains
A semiconductor relay circuit characterized by comprising: