JPH0316044B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to an electrically coupled semiconductor device in which a control section and a main drive section are electrically insulated.

[Background of the invention]

In recent years, with the development of various electronics in industry, there has been an increasing need to drive large amounts of power with even small control signals. For this kind of needs, electrical isolation of the control part and the main drive part is necessary. A typical semiconductor device that meets this need is an optical coupling device (commonly known as a photocoupler). Among them, optically coupled thyristors have blocking ability in both pure and reverse directions. It has advantages such as low power loss after switching and has a self-holding function, and is widely used in electronic exchange switches and solid state relays. However, it has some important problems. This will be explained in detail below, including the principle of operation.

FIG. 1 shows a typical basic circuit configuration using optically coupled thyristors.

When the switch 1 is closed, a current flows through the light emitting element 2 and light is emitted. This light generates a photocurrent in the photothyristor 3, and when the photothyristor is placed in a forward bias state by the AC power source 4, it is ignited by this photocurrent. In this case, since the photothyristor and the light emitting element are electrically DC-insulated, this method has the following advantages, unlike the normal electrical coupling method. Sho 5,
6 and 7 are resistances.

(a) Even if a potential difference exists between terminals B and D, control is possible, that is, ignition operation, etc. is possible.

(b) The current flowing through the light emitting element 2 does not flow into the thyristor side. Nor does the reverse occur.

On the other hand, it has the following problems.

(1) Although the photothyristor 3 and the transistor 1 are manufactured mainly using Si, the light emitting element is made using GaAs.
It is manufactured using a - group or - group compound semiconductor represented by, etc. These different materials necessitate a hybrid IC configuration, which requires precision assembly work and increases costs. The fact that the manufacturing technology for compound semiconductor wafers and their processing technology is not as good as that for Si technology also contributes to higher costs.

(2) The light emitting efficiency of the light emitting diode, the light receiving efficiency of the photothyristor, and the efficiency of transmitting light from the light emitting diode to the photothyristor are low. For this reason, the optical coupling efficiency that combines these efficiencies is small, and when driving a photothyristor, the number of light emitting elements is required.
It is necessary to flow a large control current of about mA.
Japanese Patent Publication No. 42-24863 and Japanese Patent Publication No. 53-46589 disclose embodiments in which pnpn is turned on by a MOS gate or MOS/EET. Also, in Japanese Patent Application Laid-Open No. 57-196626, there is a
An embodiment is disclosed that performs both off- and off-driving. All of these have the feature that the gate and main switch are insulated, but if the potential of the main switch is in a floating state, it cannot be turned on, that is, if the gate potential is higher or lower than the cathode potential of the main switch. It can only be turned on in one of the following cases. Therefore, it is impossible to achieve the same functionality as a photocoupler.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor device that has a monolithic structure and can isolate a control section and a main drive section in terms of direct current, and also allows control even when the potential of the main drive section is in a floating state, and can also reduce the control current. It is about providing.

[Summary of the invention]

A first feature of the semiconductor device of the present invention that achieves the above object is a semiconductor device comprising a bipolar element having at least one forward blocking junction and at least one reverse blocking junction. The object of the present invention is to include a unipolar element of one conductivity type and a unipolar element of the other conductivity type which are connected so as to short-circuit one of the elements.

In a preferred embodiment of the invention, the bipolar element is a bipolar transistor or a thyristor.

Further, in a preferred embodiment of the present invention, the semiconductor device is composed of a plurality of bipolar transistors.

Furthermore, in a preferred embodiment of the present invention, the control terminal of the one conductivity type unipolar element and the control terminal of the other conductivity type unipolar element are connected.

Furthermore, in a preferred embodiment of the invention, the unipolar element is an insulated gate field effect transistor.

Furthermore, in a preferred embodiment of the present invention, the main terminals of the unipolar element of one conductivity type and the unipolar element of the other conductivity type are connected to regions of different conductivity types of the bipolar element, or The unipolar element and the other conductive type unipolar element are connected in parallel.

Furthermore, in a preferred embodiment of the present invention, the region forming the bipolar element and the region forming the unipolar element are commonly integrated.

A second feature of the present invention is a semiconductor device including a bipolar element having at least one forward blocking junction and at least one reverse blocking junction, in which at least one of the forward blocking junctions is short-circuited. A first unipolar element of one conductivity type and a first unipolar element of the other conductivity type are connected, and a second unipolar element of one conductivity type is connected to short-circuit at least one of the reverse blocking junctions. and a conductive type unipolar element.

In a preferred embodiment of the invention, the bipolar element is a thyristor.

Further, in a preferred embodiment of the present invention, the control terminal of the first one conductivity type unipolar element and the control terminal of the first other conductivity type unipolar element are connected, and the control terminal of the first one conductivity type unipolar element is connected to The control terminal of the element and the control terminal of the second other conductivity type unipolar element are connected.

Furthermore, in a preferred embodiment of the present invention, the first one-conductivity unipolar element and the first other-conductivity unipolar element are connected in parallel, and the second one-conductivity unipolar element and the second unipolar element are connected in parallel.
is connected in parallel with the other conductivity type unipolar element.

[Embodiments of the invention]

<Example> A first example of the present invention is shown in FIGS. 2 to 4. Figure 2a is a diagram showing the basic configuration, Figure 2b is a diagram showing the connection state of Figure 2a, Figure 2c is an equivalent circuit diagram of Figures 2a and b, and Figure 3 is a diagram showing the connection state of Figure 2a. FIG. 4 is a diagram showing the basic circuit configuration corresponding to FIG. 1, and FIG. 4 is a diagram showing the symbols shown in FIGS.

In Figures 2a and b, 8 is a current control type bipolar element consisting of three layers p ₁ , n ₁ and p _2.
It is a pnp bipolar transistor (hereinafter simply referred to as a pnp transistor), in which emitter junctions p ₁ and n ₁ form a reverse blocking junction, and collector junctions n ₁ and p ₂ form a forward blocking junction. 9 is a current-controlled npn bipolar transistor (hereinafter simply referred to as npn transistor) consisting of three layers of n ₂ p ₃ n ₃ , which is a bipolar element.
, the collector junction n ₂ p ₃ forms a forward blocking junction, and the emitter junction p ₃ n ₃ forms a reverse blocking junction. here,
The base _n1 of the pnp transistor 8 and the collector _n2 of the npn transistor 9 are connected by wiring such as Al, and the collector _p2 of the pnp transistor 8 and the collector n2 of the npn transistor 9
It is connected to the base _p3 of the transistor 9 by a wiring made of Al or the like. 10 is p which becomes a unipolar element
It is a channel insulated gate field effect transistor (hereinafter simply referred to as p-channel MOS/FET),
The source and drains p ₄ and p ₅ are respectively connected to the emitter p ₁ and collector p ₂ of the npn transistor 8 by wiring made of Al or the like so as to short-circuit at least the collector junction n ₁ p ₂ . Reference numeral 11 denotes an n-channel insulated gate field effect transistor (hereinafter simply referred to as n-channel MOS/FET) which is a unipolar element, and the drain and source n ₅ and n ₆ are connected to the collector n ₂ and emitter n ₆ of the npn transistor 9 with Al. are connected to short-circuit at least the collector junction n ₂ p ₃ by wiring such as . Here, pnp transistor 8, npn transistor 9, p channel MOS・
FET10, n-channel MOS/FET11, for example, FHLEE: IEEE Transactions on Electron
Epitaxial Passivated Integrated as shown in Devices vol.ED−15, No.9, 1968, p645
It is formed independently within a single crystal island of a dielectric isolation substrate created by the circuit (EPIC) process, and as described above.
A monolithic semiconductor device is constructed by wiring with Al or the like.

In addition, in FIG. 2c, the pnp transistor 8 and p-channel MOS/FET 10 are integrated in FIG. 2b, and the npn transistor 9 and n-channel MOS/FET 11 are integrated. be.

Furthermore, in FIG. 4, the control terminals G ₁ and G ₂ are commonly connected to the switch, and the switch 1 consisting of an npn transistor and the resistors 5 and 7 are also formed in the dielectric isolation substrate and are monolithic. .

The operating principle of this embodiment will be explained using FIGS. 2 and 4.

When switch 1 is open, A ₁ and B ₁ are in a cutoff state. When switch 1 is closed, power supply 15 is activated.
A voltage higher than the threshold voltage of the MOS-FETs 10 and 11 is applied to G ₁ and G ₂ . Therefore, in a forward bias state, that is, when the potential of A ₁ is sufficiently higher than the potential of B ₁ , conduction can be established between A ₁ and B ₁ . in this case
Regardless of the potential relationship between G ₁ , G ₂ and A ₁ , B ₁ , conduction can be achieved in either case. However, when the B ₁ terminal is in an electrically floating state, the operating mechanism differs depending on the level of the potentials of G ₁ and G ₂ and the potentials of A ₁ and B ₁ , so each case will be explained in detail below.

() When the potential of G ₁ and G ₂ is lower than the potential of B ₁ and A ₁ . (For example, equivalent to when the switch 12 is turned on to the power supply 13 side) The n-channel MOS/FET 11 is off, but the p
Channel MOS/FET10 turns on. As a result, the current flows through the p-channel MOS/FET10.
The current flows to the base _p3 of the transistor 9, and the npn transistor 9 is turned on. As a result, A ₁ → emitter junction of pnp transistor 8 n ₁ p ₁ → npn transistor 9 →
Current flows through the path of B ₁ and conduction occurs between A ₁ and B ₁ .
Since the collector currents of the npn transistors 9 and 8 serve as the base current of the other transistor, if the current amplification factor of the transistors is increased, positive feedback occurs and both transistors become saturated. Therefore, deeper conduction can be achieved between A ₁ and B ₁ .

() When the potential of G ₁ and G ₂ is higher than the potential of B ₁ and A ₁ . (For example, this is equivalent to when the switch 12 is turned on to the power supply 14 side and the voltage of this power supply 14 is higher than the voltage of the AC power supply 4.) Although the p-channel MOS/FET 10 is off,
N-channel MOS/FET 11 is turned on. As a result, the base current of the pnp transistor 8 flows through the n-channel MOS/FET 11, and the pnp transistor 8 is turned on. As a result, A ₁ → pnp transistor 8 → emitter junction of npn transistor 9 p ₃ n ₃
→Current flows through the path B ₁ and conductivity occurs between A ₁ and B ₁ .
If the current amplification factor of the transistor is increased, positive feedback will occur as in (), and a deeper conduction state can be created between A ₁ and B ₁ .

() The potentials of G ₁ and G ₂ are higher than the potential of B ₁ , and A ₁
If the potential is lower than .

p channel MOS/FET10 and n channel
Both MOS and FET11 are turned on. As a result, both of the above phenomena () and () occur, and A ₁ , B ₁
Conductivity can be established between the two.

As described above, according to this embodiment, it is possible to realize an operation that can be controlled even if there is a potential difference between the control section and the main drive section.

Further, the control element of this embodiment is a MOS/FET which is a unipolar element. Therefore, as is well known, since an insulating film such as an oxide film is interposed between the gate electrode and the source/drain/channel section, it is possible to realize direct current electrical insulation between the control section and the main drive section. . This dielectric strength voltage is determined by the thickness and quality of the gate insulating film, and is usually in a contradictory relationship with the threshold voltage. However, by lowering the impurity concentration in the channel portion (e.g., approximately 1×10 ¹⁴ cm ^-3 ) and making the oxide film thicker (e.g., approximately 1 μm), a dielectric strength voltage of approximately 1000V and a threshold voltage of approximately 5V can be achieved at the same time. can.

Each element is dielectrically isolated using the EPIC process, and the insulation voltage between the elements is 1000V or more.

Furthermore, as a control current, gate capacitance (capacitance of the insulating film existing between the gate electrode and the channel part, etc.)
The displacement current required to charge and discharge is usually only a few microamperes, which is about three orders of magnitude lower than that of the optical coupling method.

In this example, when the main drive section is driven by a 100V, 10KHz AC power supply, the main drive current of 100mA can be controlled using a 5V signal power supply, and the on-voltage when conducting is approximately
The voltage is 1.4V, and the breakdown voltage between input and output is, for example, about 1000V.

As described above, according to this embodiment, the control section and the main drive section can be made of the same material and have a monolithic structure, and can be DC-insulated between them, and can be controlled with a small current.

<Example 2> FIG. 5 is a circuit diagram showing a second example of the present invention, and the elements within the broken lines are integrated into a thyristor structure that becomes a bipolar element by integrating the elements shown in FIG. Form.

That is, p emitter (p _E ) 17 is pnp in Figure 2b.
Transistor 8 p ₁ and p channel MOS/FET 1
0 p ₄ are commonly integrated, and the n base (n _B ) 16 is the same as that of the pnp transistor 8 in FIG. 2b.
n ₁ and npn transistor 9 n ₂ and p channel MOS・
n ₄ of FET10 and n ₅ of n-channel MOS/FET11
The p base (p _B ) 18 is the p ₂ of the pnp transistor 8 in FIG. 2b.
and _p3 of npn transistor 9 and p channel MOS・
p ₅ of FET10 and p ₆ of n-channel MOS/FET11
The n emitter (n _E ) 19 is the n ₃ of the npn transistor 9 in FIG. 2b.
and _n6 of n-channel MOS/FET 11 are commonly integrated. Here, the n _B p _B junction becomes a forward blocking junction, and the p _E n _B junction and the p _E n _B junction become reverse blocking junctions.

When switch 1 is open, A ₂ and B ₂ are in the off state. When the switch 1 is closed, a voltage higher than the threshold voltage is applied from the power supply 15 to the control terminals G ₃ and G ₄ . Therefore, it turns on when the AC power supply 4 puts A ₂ and B ₂ into a forward bias state. At this time, the control terminal
A ₂ and B 2 can be turned on regardless of the relationship between the potentials of the G ₃ and G ₄ terminals and the potentials of the B ₂ and _{A 2 terminals} , but the operating mechanism differs depending on the relative relationship of the potentials between the terminals. . When the potential of the G ₃ and G ₄ terminals is lower than the potential of the A ₂ and B ₂ terminals, a p channel is formed on the surface of the n _B 16 below the G ₃ electrode 15, and holes flow from p _E 17 to p _E 18. . As a result, the injection of electrons from n _E 19 to p _E is promoted, the n _E p _B n _B transistor part is turned on, and the electrons are
n Flows into _B. Therefore, the injection of holes from p _E 17 into n _E 16 is then promoted, and the p _E n _B p _E transistor portion is turned on. The collector currents of the n _E p _E n _B and p _E n _B p _B transistors mutually become the base current of other transistors, so positive feedback occurs, and eventually the thyristor p _E n _B p _E n _E is turned on. reach.

When the potential of the G ₃ and G ₄ terminals is higher than the potential of the B ₂ and A ₂ terminals, an n channel is formed on the p _B surface under the G ₄ electrode, and electrons flow from n _E 19 to n _B 16. As a result, hole injection from p _E 17 to n _B 16 is promoted.
p _E n _B p _B The transistor part turns on, and the holes p _B 18
Flow inside. Therefore, next, the injection of electrons from n _E 19 to p _B 18 is promoted and the n _E p _B n _B portion is turned on, causing the above-mentioned positive feedback and p _E n _B p _B n _E is turned on.

The potential of the G ₃ and G ₄ terminals is higher than the potential of the B ₂ terminal,
If the potential is lower than the potential of the _A2 terminal, both of the above cases occur and p _E n _B p _B n _E is turned on.

Next, the electrical characteristics and features of the semiconductor device according to this embodiment will be explained.

The forward and reverse withstand voltage between the A ₂ and _B terminals is approximately 100V.
The DC insulation voltage between the G ₃ and G ₄ terminals and the A ₂ and B ₂ terminals is approximately
It is 650V. If a 10KΩ resistor is connected between _pB and _nE to increase noise tolerance, the potential between the A ₂ and B ₂ terminals can be turned on by setting the potential of the G ₃ terminal to approximately 4V. Also, by setting the potential of _G4 terminal to approximately 7V
The A ₂ and _B terminals can be turned on. Therefore, in order to connect the G ₃ and G ₄ terminals and turn on the A ₂ and B ₂ terminals, the potential of this terminal needs to be approximately 7V. Furthermore, the potential difference between A ₂ and B ₂ when 100 mA is applied after turning on, that is, the on voltage is approximately 1.25V.

In addition to having the same features as the first embodiment, this embodiment also has the following features.

Since it has a composite integrated configuration, the occupied area is small (for example, about 300 μm x 300 μm in the case of this example).
It is suitable for being built into an IC to achieve high integration. In the case of the first embodiment, since the number of constituent elements is large and the insulation and separation between the elements also requires space, the occupied area is approximately 2.8 times larger in order to achieve almost the same characteristics.

<Embodiment 3> FIG. 6 is a circuit diagram showing a third embodiment of the present invention, in which the semiconductor device within the broken line is different from the first and second embodiments.

9 is an npn transistor serving as a bipolar element. 10 is a unipolar element and p channel
It is a MOS/FET, and the source and drain are
It is connected to the collector and base of the npn transistor 9 so as to short-circuit the collector junction, which is a forward blocking junction of the npn transistor 9. Reference numeral 11 denotes an n-channel MOS/FET serving as a unipolar element, and its source and drain are connected to the collector and base of the npn transistor 9 in parallel with the p-channel MOS/FET so as to short-circuit the collector junction of the npn transistor 9.

Each element is formed independently within a single crystal island of a dielectric isolation substrate created by the EPIC process, and wired with Al or the like.

Control terminals G ₁ and G ₂ are commonly connected to switch 1.

Each element formed within the single crystal island is a high voltage element with a withstand voltage of 250V or more. The npn transistor 8 has a well-known general structure, and is an n-channel transistor.
For example, MOS/FET9 (WHAMattheus:
Digest of ISSCC P238, Feb. 1981) is a vertical structure high-voltage MOS/FET, and the p-channel MOS/FET10 is, for example, (Yoshida et al. "High-voltage MOS/FET" Semiconductor Transistor Study Group Materials) High voltage MOS/FET with lateral structure as disclosed in SSD73-14, June 1973)
It is.

In FIG. 6, when switch 1 is open, transistor 8 is not supplied with base current even in a forward bias state and is in an off state between A ₂ and B ₂ .
Close switch 1 and connect control terminals G ₁ and G ₂ from power supply 15.
When a voltage higher than the threshold voltage of the MOS-FETs 10 and 11 is applied to the npn transistor 9, the npn transistor 9 is turned on. At this time, even if the A ₂ and B ₂ terminals are in a floating state, the power supply 20 turns on the npn transistor 9 regardless of the relationship between the potentials of the control terminals G ₁ and G ₂ and the potentials of the A ₂ and B ₂ terminals. However, the operating mechanism differs depending on the relative relationship of the potentials between the terminals.

When the potentials of the control terminals G ₁ and G ₂ are lower than the potentials of the A ₂ and B ₂ terminals, the source and drain potentials of the MOS-FETs 10 and 11 are higher than the gate potentials. Therefore, n-channel MOS/FET11 remains off, but p-channel MOS/FET1
0 turns on. As a result, p-channel MOS
The source-drain current of FET 10 flows into the base of npn transistor 9 and
turns on.

On the other hand, when the potentials of the control terminals G ₁ and G ₂ are higher than the potentials of the A ₂ and B ₂ terminals, the source/drain potentials of the MOS/FETs 10 and 11 are lower than the gate potentials. Therefore, p-channel MOS/FET
10 remains off, but the n-channel
MOS・FET11 turns on. As a result, base current is supplied to the npn transistor 9.
turns on.

The potential of control terminals G ₁ and G ₂ is higher than that of B ₂ terminal,
If the voltage is lower than the _A2 terminal, either or both of the above cases will occur and the npn transistor 9 will be turned on.

As described above, in this embodiment, the npn transistor 8 of the main drive section can be reliably driven even when the potentials of the main terminals A ₂ and B ₂ are in a floating state.

In this embodiment, the forward breakdown voltage between A ₂ and B ₂ is approximately 260V, and the insulation voltage between the A ₂ and B ₂ terminals and the control terminals G ₁ and G ₂ is approximately 600V, for example. Also, the threshold voltage when turning on is approximately 3.5V, and after turning on
For example, the on-resistance when 10mA is applied is about 15Ω.

<Example 4> FIG. 7 shows a fourth example of the present invention. It is third in that the main drive part is a high-voltage PNP transistor 8.
This is different from the embodiment. The operating mechanism is almost the same as that of the third embodiment, and the explanation of the first embodiment is omitted since it is sufficient to replace the npn transistor 9 with the pnp transistor 8.

The breakdown voltage of this embodiment is about the same as that of the third embodiment, the threshold voltage is about 4V, and the on-resistance is about 4V.
For example, it is approximately 10Ω when 3mA is applied.

<Example 5> FIG. 8 shows a fifth example of the present invention. In this embodiment, the npn transistor 9 and the pnp transistor 8 are formed in the same single crystal island to perform thyristor operation. still,
The npn transistor 9 and the pnp transistor 8 may be provided on separate single crystal islands and connected by wiring such as Al. In addition, MOS・FET10, 11
The source and drain of are npn transistors 9 and
The pnp transistors 8 are connected in parallel so as to short-circuit their respective collector junctions. Therefore, if this embodiment is replaced with the dotted line in FIG. 6 and an AC power source is connected instead of the DC power source 14, the switch 1 is closed and a forward bias voltage is applied between A ₂ and B ₂ from the AC power source. (corresponding to Figure 4), the control terminal
When G ₁ and G ₂ are lower than the A ₂ and B ₂ terminals, the p-channel MOS/FET 10 is turned on, and the npn transistor 9 and the pnp transistor 8 are driven. As a result, A ₂ ,
During _B2 , the thyristor is turned on. On the other hand, if the control terminals G ₁ and G ₂ are higher than the A ₂ and B ₂ terminals, n
The channel MOS/FET 11 is turned on, the npn transistor 9 and the pnp transistor 8 are driven, and as a result, the thyristor is turned on. This embodiment is the same as the first and second embodiments in that both transistors are driven simultaneously, and the operating mechanism is slightly different from the third and fourth embodiments.

In addition, since this example is intended for applications that use an AC power source, it is necessary to obtain forward and reverse withstand voltages, so not only the thyristor but also both n and p channel MOS/FETs 10 and 11 are used.・
It has blocking ability in both reverse directions. In other words, both the source and drain junctions were designed to withstand a voltage of 250V.

The withstand voltage between A ₂ and B ₂ in this embodiment is, for example, about 200V in both forward and reverse directions, and the A ₂ and B ₂ terminals and the control terminals G ₁ and G ₂
The dielectric strength between the two is, for example, approximately 700V. or
The threshold voltage when turning on between A ₂ and B ₂ is, for example, about 4V, and the on-resistance between A ₂ and B ₂ when 30 mA is applied is, for example, about 5.5Ω.

<Example 6> FIG. 9 shows a sixth example of the present invention. pnp transistor 8, npn transistor 9, first p-channel MOS/FET 10, and first n-channel
The MOS/FET 11 is connected and configured in the same manner as shown in FIG. The sources and drains of the second p-channel MOS/FET 21 and the second n-channel MOS/FET 22 are connected to the base of the npn transistor 9 (the pnp transistor 8 collector)
and the emitter are connected in parallel. The control terminal of the first p-channel MOS transistor 10 and the control terminal of the first n-channel MOS transistor 11 are commonly connected to form a control terminal _G3 , and
The control terminal of the second p-channel MOS transistor 21 and the second n-channel MOS transistor 22
It is connected in common with the control terminal _G4 .

A first n-channel MOS/FET 11 whose gate is connected to the control terminal _G3 and a first p-channel
The MOS/FET 10 is used to turn on the thyristor between the A ₂ and B ₂ terminals. On the other hand, control terminal G ₄
A second n-channel MOS whose gate is connected to
FET22 and second p-channel MOS/FET21
is used to turn off this thyristor.
A typical operation sequence of this embodiment is as follows.

Apply forward bias between A ₂ and B ₂ .

Apply an on control voltage to the control terminal _G3 to turn on the thyristor.

The ON control voltage at the control terminal _G3 is removed to keep the thyristor in the ON state.

An off control voltage is applied to the control terminal _G4 to turn off the thyristor.

The off control voltage at the control terminal _G4 is removed to maintain the off state of the thyristor.

The on-time operation mechanism of this embodiment, which causes such an operation, is exactly the same as the fifth embodiment, so a description thereof will be omitted, and the off-time operation mechanism will be described below. In this embodiment, when the thyristor is on, the potential of the A ₂ and B ₂ terminals is floated by applying an off control voltage higher than the threshold voltage of the MOS/FETs 21 and 22 to the control terminal G ₄ . OFF control is possible even in this state. However, the off-operation mechanism differs depending on the level relationship between the potential of the control terminal G ₄ and the potentials of the A ₂ and B ₂ terminals.

When the potential of the control terminal G ₄ is lower than the potential of the A ₂ and B ₂ terminals, the source and drain potentials of the MOS-FETs 21 and 22 are higher than the gate potential.
Therefore, the second n-channel MOS/FET 22 remains off, but the second p-channel MOS/FET 22 remains off.
21 turns on. This p-channel MOS/FET2
If the on-resistance of 1 is made sufficiently small, it will be the same as when the emitter junction of the npn transistor portion 9 of the thyristor is short-circuited. In other words, the current flowing through the thyristor is extracted and the thyristor is turned off. On the other hand, if the potential of the control terminal G ₄ is higher than the potential of the A ₂ and B ₂ terminals, the second p-channel MOS
FET21 is off, but the second n-channel
Since the MOS/FET 22 is turned on and the emitter junction of the npn transistor portion 9 of the thyristor is short-circuited, the thyristor can be turned off. The potential of control terminal G ₄ is
If the potential is higher than the potential of the _B2 terminal and lower than the potential of the _A2 terminal, either or both of the above cases will occur and the thyristor can be turned off.

As described above, in this embodiment, even when the potentials of the main terminals A ₂ and B ₂ are in a floating state, on/off driving is possible reliably. However, for on control
MOS/FETs 10 and 11 can normally be easily controlled on even if their on-resistance is relatively large, but MOS/FETs 21 and 22 for off control have relatively small on-resistance (approximately
500Ω or less).

The breakdown voltage and on-state threshold voltage of this embodiment are almost the same as those of the fifth embodiment. The voltage applied to the control terminal _G4 required to turn it off is, for example, about 6V.
Note that the on-resistance is, for example, approximately 8Ω when 30mA is applied.

<Embodiments 7 and 8> A seventh embodiment of the present invention is shown in FIG. 10, and an eighth embodiment is shown in FIG. 11, respectively. Figure 10 and 1
In each figure, there is another junction in series with the collector junction of the transistor, that is, a pnp transistor 8.
After connecting the emitter junction of the npn transistor 9 or the emitter junction of the npn transistor 9, connect the n-channel MOS/FET 11 and the p-channel MOS/FET in parallel.
10 are connected. These operating mechanisms are substantially the same as when they are connected in parallel so that only the collector junctions are short-circuited. In other words, the case in FIG. 10 is the same as the third embodiment, and the case in FIG. 11 is the same as the fourth embodiment. The difference is that after the transistor is driven, positive feedback occurs between the npn and pnp transistors. The only difference is that it turns on as a thyristor.

Although the details of the present invention have been described above using examples, the present invention is not limited to these examples and can be modified and applied in various ways.

Figure 2b, Figure 8, Figure 9, Figure 10, Figure 11
In the figure, the base n ₁ of the pnp transistor 8 and
Collector n ₂ of npn thyristor 9 and pnp
A thyristor may be formed by integrating only the collector _p2 of the transistor 8 and the base _p3 of the npn transistor 9.

For example, the devices shown in Figures 2, 8, 9, 10, and 11 are reverse blocking switches that can only be turned on when forward biased in the case of AC drive. By configuring the switch to be connected to a bidirectional switch, a bidirectional switch can be used, and the efficiency of using AC power can be improved.

Further, the semiconductor devices shown in FIGS. 2 and 8 to 11 do not have sufficient resistance to voltage noise in the forward bias direction. It goes without saying that by adding the voltage noise protection circuit disclosed in Japanese Patent Publication No. 53-46588 to the above-described embodiment, the noise resistance can be greatly improved without detracting from the features of the present invention.

In addition, a second p for off control as shown in FIG.
Channel MOS/FET21 and second n-channel
MOS/FET22 in Figure 2, Figure 5, Figure 10,
Off control may be performed by connecting at least one of the reverse blocking junctions of the bipolar element shown in FIG. 11 and the like to be short-circuited.

〔Effect of the invention〕

As described above, the present invention enables a current-controlled bipolar element to be controlled by a voltage-controlled unipolar semiconductor element, so that the monolithic structure can isolate the control part and the main drive part in terms of direct current, and the potential of the unipolar element can flow. Even in a tying state, the control can be performed reliably, and the control current can also be made small.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional example, FIGS. 2, 3, and 4 are diagrams showing a first embodiment of the present invention, and FIG. 5 is a diagram showing a second embodiment of the present invention. , FIG. 6 shows a third embodiment of the invention, FIG. 7 shows a fourth embodiment of the invention, and FIG. 8 shows a fifth embodiment of the invention.
FIG. 9 is a diagram showing a sixth embodiment of the invention, FIG. 10 is a diagram showing a seventh embodiment of the invention, and FIG. 11 is a diagram showing an eighth embodiment of the invention. It is a figure which shows an example. 8...pnp transistor, 9...npn transistor,
10, 21...p channel MOS/FET, 11, 2
1...n channel MOS/FET.

Claims (1)

[Claims] 1. A bipolar element having at least one forward-blocking junction and at least one reverse-blocking junction, and a one-side conductivity type unipolar element connected to short-circuit the forward-blocking junction of the bipolar element. 1. A semiconductor device, characterized in that the unipolar element of one conductivity type is connected in parallel with the unipolar element of the other conductivity type. 2. A semiconductor device according to claim 1, wherein a control terminal of the unipolar element of one conductivity type and a control terminal of the unipolar element of the other conductivity type are electrically connected. 3. In claim 1 or 2, the bipolar element is one bipolar transistor, two transistors connected to perform positive feedback operation.
A semiconductor device characterized by being an element selected from bipolar transistors and thyristors. 4 a bipolar element having at least one forward blocking junction and at least one reverse blocking junction; a first one-side conductivity unipolar element connected to short-circuit at least one of the forward blocking junctions of the bipolar element; a second one-side conductivity type unipolar element and a second other-side conductivity type unipolar element connected to short-circuit at least one of the reverse blocking junctions of the bipolar element; A semiconductor device characterized by: 5 In claim 4, the control terminal of the first one-way conductivity type unipolar element and the first
A semiconductor device characterized in that a control terminal of the other conductivity type unipolar element, and a control terminal of the second one conductivity type unipolar element and a control terminal of the second other conductivity type unipolar element are electrically connected to each other. . 6. The semiconductor device according to claim 4 or 5, wherein the bipolar elements are two bipolar transistors or thyristors connected to perform positive feedback operation. 7 A bipolar element in which a pnp transistor part and an npn transistor part are connected to cause positive feedback, a p channel MOS transistor connected between the emitter and collector of the pnp transistor part, and an emitter and collector of the npn transistor part. What is claimed is: 1. A semiconductor device comprising: an n-channel MOS transistor connected between the semiconductor device and the n-channel MOS transistor; 8. The semiconductor device according to claim 7, wherein the bipolar element is a thyristor.