JPS58102538A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58102538A JPS58102538A JP56201225A JP20122581A JPS58102538A JP S58102538 A JPS58102538 A JP S58102538A JP 56201225 A JP56201225 A JP 56201225A JP 20122581 A JP20122581 A JP 20122581A JP S58102538 A JPS58102538 A JP S58102538A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- region
- epitaxial layer
- type
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
本発IRは半導体装置の製造方法に係り、特にイソブレ
ーナ(1so−pxanar)技術による分離用酸化膜
の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present IR relates to a method for manufacturing a semiconductor device, and in particular to a method for forming an isolation oxide film using iso-pxanar technology.
−−*の前半分離技術に、酸化膜を
利用したイソブレーナ技術がある。この技術は基板上に
形成したエピタキシャル層を選択酸化し、厚い酸化膜に
よりエピタキシャル層を囲むことで素子分離を行なうも
のである。このイソプレーナ技術の問題点は、厚匹酸化
膜の下にn型の反転層が形成され、十分な素子分離が達
成できない点にある。その丸め従来において、厚い酸化
膜の下にチャネルカット用のP型領域を形成する等の提
案があるが、いずれも工程が煩雑で実用的ではなかつ九
〇
本発明の目的はチャネルカット領域を有する酸化膜の素
子分離構造を容易に形成することができる製法を提供す
ることにある〇
本発明の製造方法は、表面が(1,0,0)面である一
導電型の半導体基板表面ycv型溝を形成して(1,l
、 l )面金露出させる工程、ジクロールシラン(B
IH* Ok )ガスを用い九エピタ中シャル成長によ
り骸基板表面上に一導電型のエビタキシャ、ル層を形成
する工程、選択酸化により該vm溝上のエピタキシャル
層を酸化し、該vm溝先端部を除いて酸化膜とする工程
、該酸化膜により囲まれる領域に各種素子を形成する工
程とを有すること1%黴とする。--The first half of * separation technology includes isobrener technology that uses oxide films. This technique selectively oxidizes an epitaxial layer formed on a substrate, and isolates elements by surrounding the epitaxial layer with a thick oxide film. The problem with this isoplanar technology is that an n-type inversion layer is formed under a thick oxide film, making it impossible to achieve sufficient device isolation. Rounding Up Conventionally, there have been proposals to form a P-type region for channel cutting under a thick oxide film, but both require complicated processes and are not practical. The purpose of the manufacturing method of the present invention is to provide a manufacturing method that can easily form an oxide film element isolation structure. Form a groove (1, l
, l) Step of exposing the surface metal, dichlorosilane (B
A step of forming an epitaxial layer of one conductivity type on the surface of the skeleton substrate by epitaxial growth using IH*Ok gas, oxidizing the epitaxial layer on the VM groove by selective oxidation, and forming the tip of the VM groove. It is defined as 1% mold to have the steps of forming an oxide film by removing the oxide film, and forming various elements in the region surrounded by the oxide film.
以下本発明の一実施例を図面に従って詳述する。An embodiment of the present invention will be described in detail below with reference to the drawings.
本発明はジクロールシランガス(sin、at、)を用
いてエピタキシャル成長させると、結晶面が(1,0,
0)上には遅く、(1,1,1)上には速く成長すると
いう性質を積極的に利用したものである。In the present invention, when epitaxial growth is performed using dichlorosilane gas (sin, at,), the crystal plane is (1,0,
This actively utilizes the property that growth is slow on 0) and fast on (1, 1, 1).
第1図参照
allのシリコン牛導体基板1表面全面にNl1l!不
純物(例えばAs、Nb等)を高濃度に注入しn十す領
域2tl−形成する。そして周知の異方性エツチングに
より基板表面を選択的にエツチングし、(1゜1.1)
面が露出されるまでエツチングすることでvII溝3t
−形成する。 コア7) V !Ml @ 3は、n十
す領域2を分離するに十分な深さを有する。なお、n十
す領域2の一部に燐(1’)f注入し領域2′ヲ形成し
ておく。Refer to Figure 1, Nl1l is applied to the entire surface of the silicon conductor substrate 1! Impurities (for example, As, Nb, etc.) are implanted at a high concentration to form a region 2tl-. Then, the substrate surface is selectively etched by well-known anisotropic etching (1°1.1).
Etch the vII groove 3t until the surface is exposed.
- form. Core 7) V! Ml@3 has sufficient depth to separate n+ regions 2. Incidentally, phosphorus (1')f is implanted into a part of the n+ region 2 to form a region 2'.
第2!gl参照
反応ガスとしてd、、 B、H,、81H,Ot、(ジ
クロールシラン)を用いて基板上全面にPa11!のエ
ピタキシャル層重を成長する。このジクロール/ランを
用いたエピタキシャル成長は、例えば七ノシラン(8i
H,)や四塩化ケイ素(si(3t4)’を用いた成長
に比べ、(1,0,0)面上で遅<(1,−1,1)面
上で速匹という成長速度の選択性を有するため、vg溝
3上では成長速度大で、エピタキシャル層重の表面は、
vm溝3上でもゆるやかな 。Second! Using d,, B, H,, 81H, Ot, (dichlorosilane) as the gl reference reaction gas, Pa11! was applied to the entire surface of the substrate. Grow epitaxial layers. Epitaxial growth using this dichlor/ran can be performed, for example, with heptanosilane (8i
Compared to growth using H,) or silicon tetrachloride (si(3t4)'), the growth rate is slower on the (1,0,0) plane and faster on the (1,-1,1) plane. Because of this, the growth rate is high on the VG groove 3, and the surface of the epitaxial layer is
Even on vm groove 3 it is gentle.
面となる。It becomes a surface.
@3図参照
全面に耐酸化性の膜として811N4膜5を形成し、V
型溝上を除去する。そして酸化雰囲気中にてvti溝上
のエピタキシャル層4を酸化する。■型溝3の端部(片
の部分)上のエピタキシャル項番の膜厚はvm溝3の底
部上のそれより小であるため、エピタキシャル層4を表
面からn+b 領域2に達するよう酸化しても底部に
Fip型のシリコン領域4′が残る。@See Figure 3 An 811N4 film 5 is formed as an oxidation-resistant film on the entire surface, and V
Remove the top of the mold groove. Then, the epitaxial layer 4 on the VTI trench is oxidized in an oxidizing atmosphere. ■Since the thickness of the epitaxial layer on the end (piece part) of the mold groove 3 is smaller than that on the bottom of the vm groove 3, the epitaxial layer 4 is oxidized from the surface to reach the n+b region 2. Also, a Fip type silicon region 4' remains at the bottom.
第4図参照
81、N4膜5を除去したのち、酸化膜6によりSまれ
た領域に各種の素子を形成する。本実施例ではnfiの
工ばツタ領域ツ、コレクタ領域8t−形成し、P型のエ
ピタキシャル層4をペース領域として利用している0そ
の後エミッタ電極9、ペース電極10、コレクタ電極1
1t−設ける。Referring to FIG. 4 81, after removing the N4 film 5, various elements are formed in the region surrounded by the oxide film 6. In this embodiment, an ivy region 8T and a collector region 8T are formed in the NFI process, and the P-type epitaxial layer 4 is used as a space region.
1t-provided.
本実施例によれば、分離構造が酸化膜6とv3擲底部に
残したpgシリコン領域lとで構成される。そしてその
製造工程は、V型溝3上に成長するエピタキシャル層重
が、ジクロール/ラ/ガスを用いた成長であるため、そ
の選択性によりV型!3上で4工ピタキシヤル層4はほ
ぼ平担に形成されるので、例えば従来の表面を削ったり
する工程は不要である。According to this embodiment, the isolation structure is composed of the oxide film 6 and the pg silicon region l left at the bottom of the v3. In the manufacturing process, the epitaxial layer grown on the V-shaped groove 3 is grown using dichlor/ra/gas, and its selectivity makes it V-shaped! Since the four-layer pitaxial layer 4 is formed substantially flat on the surface of the layer 3, the conventional process of scraping the surface, for example, is not necessary.
以上説明したように本発明によれば、きわめて簡単な工
程で素子分離構造を形成することができるOAs explained above, according to the present invention, an element isolation structure can be formed in an extremely simple process.
第1乃至4図は本発明の一実施例の製造工程断面図であ
る。1 to 4 are cross-sectional views of the manufacturing process of one embodiment of the present invention.
Claims (1)
面KVtlNllfr形11テ(1,1,1)Iit露
出させる工程、 ジクロールシラン(81H,ot*)ガスを用い九エピ
タキシャル成長により該基板表面上に一導電一のエピタ
キシャル層を形成する工程、選択酸化により該vm溝上
のエピタキシャル層を酸化し、該vtm溝先端部を除い
て酸化膜とする工程、 該酸化膜により囲まれる領域に各種素子を形成する工程
とを有すること全4I黴とする半導体装置の製造方法。[Claims] A step of exposing a surface of a semiconductor substrate of one conductivity type having a (1,0,0) plane KVtlNllfr type 11te(1,1,1)Iit, dichlorosilane (81H,ot*) a step of forming a conductive epitaxial layer on the surface of the substrate by epitaxial growth using a gas; a step of oxidizing the epitaxial layer on the VTM groove by selective oxidation to form an oxide film except for the tip of the VTM groove; A method for manufacturing a semiconductor device comprising the step of forming various elements in a region surrounded by an oxide film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56201225A JPS58102538A (en) | 1981-12-14 | 1981-12-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56201225A JPS58102538A (en) | 1981-12-14 | 1981-12-14 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58102538A true JPS58102538A (en) | 1983-06-18 |
Family
ID=16437405
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56201225A Pending JPS58102538A (en) | 1981-12-14 | 1981-12-14 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58102538A (en) |
Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01270644A (en) * | 1988-04-22 | 1989-10-27 | Canon Inc | Particle analyser |
US5909278A (en) * | 1996-07-29 | 1999-06-01 | The Regents Of The University Of California | Time-resolved fluorescence decay measurements for flowing particles |
JPH11264834A (en) * | 1997-12-10 | 1999-09-28 | Peter Heiland | Raster mode scanning apparatus for compensating disturbance effect of mechanical vibration affecting scanning step |
US6137584A (en) * | 1996-11-27 | 2000-10-24 | Max-Planck-Gesellschaft Zur | Method and device for determining predetermined properties of target particles of a sample medium |
JP2002022773A (en) * | 2000-05-17 | 2002-01-23 | Tektronix Inc | Measuring instrument and oscilloscope |
US6664528B1 (en) * | 2001-07-06 | 2003-12-16 | Palantyr Research, Llc | Imaging system and methodology employing reciprocal space optical design |
JP2005512086A (en) * | 2001-12-11 | 2005-04-28 | アマシャム バイオサイエンス ユーケイ リミテッド | System and method for multi-photon counting with time correlation |
US20050230610A1 (en) * | 2004-04-14 | 2005-10-20 | Leica Microsystems Cms Gmbh | Microscope for investigating the lifetime of excited states in a sample |
JP2006227013A (en) * | 1998-05-14 | 2006-08-31 | Luminex Corp | Flow analyzer and multi-analyte diagnostic system |
US20070057198A1 (en) * | 2003-07-17 | 2007-03-15 | Tony Wilson | Apparatus for and method of measuring flourescence lifetime |
JP2007323061A (en) * | 2006-05-31 | 2007-12-13 | Carl Zeiss Microimaging Gmbh | Laser scanning microscope associated with fast data processing |
JP2008015492A (en) * | 2006-07-01 | 2008-01-24 | Carl Zeiss Microimaging Gmbh | Method and arrangement for detecting light signals |
JP2008032440A (en) * | 2006-07-26 | 2008-02-14 | Hokkaido Univ | Device and method for measuring emission life |
JP2009258746A (en) * | 2001-07-06 | 2009-11-05 | Palantyr Research Llc | Imaging system and methodology employing reciprocal space optical design |
JP2010509570A (en) * | 2006-11-03 | 2010-03-25 | パーデュー・リサーチ・ファウンデーション | Ex vivo flow cytometry method and apparatus |
JP2010193544A (en) * | 2009-02-16 | 2010-09-02 | Ricoh Co Ltd | Device and method for sequence measurement |
WO2011135618A1 (en) * | 2010-04-27 | 2011-11-03 | Hitachi, Ltd. | Mainframe storage apparatus that utilizes thin provisioning |
-
1981
- 1981-12-14 JP JP56201225A patent/JPS58102538A/en active Pending
Patent Citations (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01270644A (en) * | 1988-04-22 | 1989-10-27 | Canon Inc | Particle analyser |
US5909278A (en) * | 1996-07-29 | 1999-06-01 | The Regents Of The University Of California | Time-resolved fluorescence decay measurements for flowing particles |
US6137584A (en) * | 1996-11-27 | 2000-10-24 | Max-Planck-Gesellschaft Zur | Method and device for determining predetermined properties of target particles of a sample medium |
JP2001509255A (en) * | 1996-11-27 | 2001-07-10 | マックス−プランク−ゲゼルシャフト ツル フェルデルング デァ ヴィッセンシャフテン エー.フォオ.,ベルリン | Method and apparatus for determining predetermined properties of target particles in a sample medium |
JPH11264834A (en) * | 1997-12-10 | 1999-09-28 | Peter Heiland | Raster mode scanning apparatus for compensating disturbance effect of mechanical vibration affecting scanning step |
JP2006227013A (en) * | 1998-05-14 | 2006-08-31 | Luminex Corp | Flow analyzer and multi-analyte diagnostic system |
JP2002022773A (en) * | 2000-05-17 | 2002-01-23 | Tektronix Inc | Measuring instrument and oscilloscope |
JP2009258746A (en) * | 2001-07-06 | 2009-11-05 | Palantyr Research Llc | Imaging system and methodology employing reciprocal space optical design |
US6664528B1 (en) * | 2001-07-06 | 2003-12-16 | Palantyr Research, Llc | Imaging system and methodology employing reciprocal space optical design |
US20050256650A1 (en) * | 2001-12-11 | 2005-11-17 | Rudi Labarbe | System and method for time correlated multi-photon counting measurements |
JP2005512086A (en) * | 2001-12-11 | 2005-04-28 | アマシャム バイオサイエンス ユーケイ リミテッド | System and method for multi-photon counting with time correlation |
US20070057198A1 (en) * | 2003-07-17 | 2007-03-15 | Tony Wilson | Apparatus for and method of measuring flourescence lifetime |
JP2007530916A (en) * | 2003-07-17 | 2007-11-01 | アイシス イノベイシヨン リミテツド | Apparatus and method for measuring fluorescence lifetime |
US20050230610A1 (en) * | 2004-04-14 | 2005-10-20 | Leica Microsystems Cms Gmbh | Microscope for investigating the lifetime of excited states in a sample |
JP2007323061A (en) * | 2006-05-31 | 2007-12-13 | Carl Zeiss Microimaging Gmbh | Laser scanning microscope associated with fast data processing |
US20080007820A1 (en) * | 2006-05-31 | 2008-01-10 | Gunter Moehler | Laser scanning microscope with high-speed data processing |
JP2008015492A (en) * | 2006-07-01 | 2008-01-24 | Carl Zeiss Microimaging Gmbh | Method and arrangement for detecting light signals |
US7859673B2 (en) * | 2006-07-01 | 2010-12-28 | Carl Zeiss Microimaging Gmbh | Method and arrangement for detecting light signals |
JP2008032440A (en) * | 2006-07-26 | 2008-02-14 | Hokkaido Univ | Device and method for measuring emission life |
JP2010509570A (en) * | 2006-11-03 | 2010-03-25 | パーデュー・リサーチ・ファウンデーション | Ex vivo flow cytometry method and apparatus |
JP2010193544A (en) * | 2009-02-16 | 2010-09-02 | Ricoh Co Ltd | Device and method for sequence measurement |
WO2011135618A1 (en) * | 2010-04-27 | 2011-11-03 | Hitachi, Ltd. | Mainframe storage apparatus that utilizes thin provisioning |
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