JPS5810252A - Address designation device for memory - Google Patents

Abstract

PURPOSE:To simplify a processing program and to decrease the memory capacity, by introducing an absolute address from the 2nd absolute address, based on the information discriminating the 1st absolute address and a terminal device fixedly set. CONSTITUTION:A storage area (page) for the data processing by a terminal device of an RAM 30 is designated for the address with, e.g., 8-digit figure and address designation is made with the combination of the absolute address consisting of a figure of upper-order 2-digit and a relative address consisting of a figure of lower-order 2-digit. An interruption request signal terminal of an interruption code converting circuit 14 is connected to an interruption request signal input terminal of a CPU 11. The interruption code conversion circuit 14 provides an interruption request signal INT to the CPU 11 when the interruption request is given from transmission control circuits 151-15N to give a code discriminating a terminal device based on the interruption request from any terminal device to a page code conversion circuit 20.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory specification device, and more particularly, to a memory specifying device that connects a plurality of terminals in common to a central processing unit and specifies the address of the memory included in the central processing unit based on an interrupt from the terminal. The present invention relates to a memory addressing device that performs addressing by a combination of absolute addresses and relative addresses.

Generally, systems are known in which a plurality of terminals are commonly connected to a central processing unit and data is transmitted between each terminal and the central processing unit. The central processing unit has a built-in memory that includes a terminal identification storage area used for data processing of each terminal identification.

The storage area for terminal identification included in this memory is sometimes called a page. Then, when an interrupt request is received from a terminal, the central processing unit determines which terminal the interrupt request came from (in other words, the terminal number "i" that made the interrupt request).
Then, address data for specifying the n1 memory area (page) of the memory according to the terminal device is output 7, and the address of the memory is specified based on the calculated address data. In other words, in a system in which multiple terminals are commonly connected to a central processing unit, it is necessary to perform the conventional memory addressing, terminal number determination operations, and address calculation operations according to the terminal number. Therefore, 70 grams were required for analysis. As a result, the program for addressing becomes complicated, and the storage capacity of the 10-gram memory for storing the complicated program increases, making it expensive.

Therefore, an object of the present invention is to provide a system in which a plurality of terminals are commonly connected to a central processing unit and a shared memory included in a medium-heat processing unit is commonly used by the plurality of terminals. To provide a memory addressing device which is improved so that a program for specifying a memory address can be simplified, the storage capacity of a memory for storing the program can be reduced, and addresses can be specified at low cost. That's true.

To summarize the invention, the memory storage area is divided into each terminal device. The address for specifying the storage area corresponding to each terminal device is specified by an absolute address in which the upper digits of address data consisting of a plurality of digits are used. In the absolute address, a part of the number of bits is fixedly set by the hardware circuit, and the remaining number of bits is derived by the conversion means based on the code including 111 from the terminal. Based on the combination of the fixedly set first absolute address and the second absolute address converted by the conversion means, the address of the area or page corresponding to the terminal is specified.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a system in which AI terminals are connected to a central processing unit WVC according to an embodiment of the present invention. In the figure, a plurality of terminals l to N are commonly connected to a medium heat treatment device lO via a transmission line. Famous terminal 1-
Terminal numbers are determined for N and VJll, respectively.

The central processing unit i, I Oij, arithmetic processing unit or microb includes CPUII of ``3+Yanato''.CPU
11 to 11, a read-only read-only sled (hereinafter referred to as 1-'ROM) 1g, a base code conversion circuit 2o, which is an example of an absolute address data derivation means, and a random access memory (hereinafter referred to as RAM) 80 are connected to each other via a path line I2. It will be done. ROM 1 a tJ%CPU 11 is terminal l~
A transmission control program for data transmission with N is preset and stored. Details of the page code conversion circuit 2° will be explained with reference to FIG. 2, which is described above. R
AM 80 tJ% This is a shared memory commonly used by a plurality of terminals 1-H. The RAM 30 includes a storage area (that is, a page area) necessary for each terminal to perform decryption processing and a transmission buffer used for data transmission between terminals, as well as various other types of storage. Contains areas.

This storage area for data processing of the terminal equipment in RAM 3 (l) is also called a page. The name page in RAM 80 is addressed by an 8-digit number, for example, and 2 digits in the tens place. Absolute address consisting of numbers and lower 2
Addressed by a relative address combination of digits. However, in this embodiment, one digit of the address is shown in hexadecimal notation.The storage area of the RAM 80 and the relationship between absolute addresses and relative addresses will be explained in detail in FIGS. 3A to 8C below. .

An interrupt code conversion circuit 14 is connected to the basic code conversion circuit 20 via a path line 12'.

If the pass line 12' has less than 16 terminals, it is an 8-bit line. The interrupt request signal deriving terminal of the interrupt code conversion circuit 14 is connected to the interrupt request signal input terminal of the CPU It. This interrupt code conversion circuit 14
6. Transmission control circuit 151 corresponding to the terminals l to N
-IFIN is connected. 14 interrupt code conversion circuits,
When there is an interrupt request from each transmission control circuit 151-15N, an interrupt request signal INT is given to the CPU II, and a code for identifying the terminal (i.e., the terminal A code for identifying the machine serial number) is given to the base code conversion circuit 2o. Terminals 1 to N are connected to the transmission control circuits 151 to 15N via corresponding transmission lines, respectively. 1゜wJ2 Figure 1 shows an interrupt code conversion circuit 1 which is a feature of the present invention.
Detailed circuit diagram of 4 and page code conversion circuit 2()'
``C.'' In the configuration, the interrupt code conversion circuit 14,
When an interrupt request is received from any terminal, a second interrupt request signal INT is given to the CPU 11. Upon arrival, the interrupt code conversion circuit 14 converts the interrupt code into a conversion circuit 21, which is an example of a conversion means, based on which terminal received the interrupt request.
and multiple setting switches 228 - 227 and resistors 288 ~
Contains 237.

Specifically, the upper pins of the Yss conversion circuit 21) A3 to A
Each of the 7 input terminals has a corresponding setting switch 223.
~227 to ground. Moreover, the input terminals of A3 to A7 are connected to a power supply voltage (10V) via corresponding resistors 288 to 287, respectively. The input data of this conversion circuit 21 is the top 5 bits) A3 to A7 are switches 228
~2270 (determined by on/off state switching, lower 8 bits) AO~A2 are configured by the terminal equipment code given from the interrupt code conversion circuit 14.

FIGS. 3A to 3C are diagrams schematically showing the storage area of the FiRAM 80. Particularly, FIG. 3A shows the relationship between the storage area of the terminal device included in the RAM 3Q, that is, the address of the page. RAM 80 includes a relatively large number of storage areas, each of which is addressed by a four-digit value in hexadecimal notation. Then, the storage area corresponding to one terminal device, that is, the address number of one page is expressed in hexadecimal FF.
(However, p-16), there are 8 terminals (N = 8), and the page corresponding to terminal 1 is 800 in hexadecimal representation.
When pruning starts from address 0, the address of the page corresponding to each terminal is determined as follows. In other words, the page $0 [, 8000 to 8 in hexadecimal notation corresponding to terminal l
It is designated by address 9FF. Page corresponding to terminal 2 #
1 is specified by FF addresses 8100 to 81 in hexadecimal notation. Similarly, page #2 corresponding to terminals 8 to 8
~#7 tj: The second digit from the top of s is the number corresponding to the page number.

Next, the relationship between the basic code conversion circuit 20 and the storage area of the RAM 80 will be explained. RA1 corresponding to terminals 1 to 8
If the storage area (page) of 11180 starts from an address in the middle (in the illustrated example, the absolute address is 80), the absolute address of the lower two digits is calculated based on the interrupt code from the terminal device. Must. However, in this embodiment, pages assigned to each terminal are set by a hardware circuit based on the switching states of the switches 228-227. For example, following the previous example, the upper digits of the absolute addresses of pages #0 to #7 are 8, so
Only the switch 227 shown in FIG. 2 is open (ie, turned off), and the other switches 228 to 226 are closed (ie, turned off), respectively.
i.e. turned on). Therefore, A of the conversion circuit 21
If the input of bits 3 to A6 is logic "0", A? The input of the bit becomes logic "l".

Figure 8B shows terminal F! ! 1 shows the relationship between pages #0 to #7 included in the RAM 80 corresponding to pages 1 to 8 and absolute addresses. FIG. 8C is a diagram schematically showing the storage contents of the storage area specified by the relative address of one page. In FIGS. 3B and 8C, RAMgO
Each storage area is addressed by a four-digit number in hexadecimal notation. Of address data consisting of four digits expressed in hexadecimal, the upper two digits are an absolute address υ, and the lower two digits are a relative address. One digit of this absolute address is fixedly determined by the on-on state of the switches 228 to 2270, and the lower one digit of the absolute address is determined by a code that identifies the terminal that has made the interrupt request.

The relative address is determined based on an instruction (command) for performing an operation of the CPU II. Even if [r, the relative address of the lower two digits is 110 to 3F in 16 quasi-display, the area for storing the address of the division control circuit is specified)1
~ru. Relative address of lower two digits 40~qF-c received light r
Noraku storage area is specified.

The thief uses the relative address 80 to BF of the lower two digits to become the receiver 1i buffer. −
R Go☆ 2-digit relative address COCZ/ζ, Cif
, l In hexadecimal notation, 12) to b'li' specifies the ir4 storage area that will become the transmission buffer. Each storage area pointed to by this relative address ()0 to 14'' is included in the name page #u=x't.

FIG. 4 shows the operation of this implementation fllJ. Next, the specific operation of this launch ψi will be explained with reference to FIGS. 1 to 4.

When an interrupt request is transmitted from a terminal device ('f?: even θ゛ terminal device 1), the interrupt request signal is sent to the 10 interrupt code conversion circuit 14 via the transmission control circuit 151. The interrupt code conversion circuit 14 sends an interrupt request signal IN'l'' (1-CPU 11) and outputs one interrupt request to the CPU 11. The code [0 (IIJ) is converted to pI approximately 2I by θλ. At this time, when there are interrupt requests from multiple terminals 1 to 8, page #() to page #7 corresponding to each terminal is For the kth specified,
Switch 227 is opened in advance and other switches 223 are opened.
~226 are closed. However, the conversion circuit 21
RAM 3 corresponding to the terminal 1 that received the 11 interrupt request.
As an absolute address that specifies page #0 of 0, c
161G k shows the absolute addressing data of r80J and gives it to CP[JIl.

This includes 1, 7-1 CPU 111 (J step 4
1, the page register containing the page code (
Loading into the diagram -1 (-zu) 3, followed by step 4
2 smell'n, CI) Ull N transmission control circuit 15
Read the given take from 1 to the absolute address l'-
g (The CPU 11 specified in IJ has the absolute address ``80'' and the receive buffer with the relative address ``80-1'' and writes the transmitted take4'ro.)Next, in step 44, the CPU r 80 j
and relative address r4 (IJ) specifies the reception completion flag area and sets the reception completion flag to 1. After that, the process based on the interrupt request from the CPU 11μ end Miiso 1 is terminated, and - On the other end A, the operation when there is a small interrupt request is given to υ... Like Lee 1, to the invention of - V, there are multiple d1 corresponding to the terminal. Based on the first 4'/, χ, set on the 1h' constant plane and the second absolute address based on the 1 positive information that identifies the terminal. Since the absolute address is determined, V based on the terminal's interrupt request
・So, it is necessary to perform the address.
Processing for this purpose] 1.1 graph i- can be simplified, the memory required for its block Wr, 'tt; (The effect of t+!J' such as -(゛kii)) is produced by specifying the address of the memory.

[Brief explanation of drawings]

1st L\I P;l This prayer is a flock diagram of the Ming Ichijo example. FIG. 2 is a detailed diagram of the interrupt code conversion circuit and the page code conversion circuit of the present invention. 3rd Al request 1 - 3rd C Figure l RAM 80 storage area L 1 wt + (ij 1 ~ t (doji C'', a). Figure 4 1 Based on interrupt request (of CPU II processing program) This is a p-chart. In the figure, % ]-N terminals, 10 is a central processing unit,
l HJ: CPU, 12 is pass line, 18 is R
OM, 14 is an interrupt code conversion circuit, 151 to 15N are transmission control circuits, 20ij, basic code conversion circuit, 21
ij: conversion circuit, 223-227 setting switch as an example of setting means, 288-287t, 1:'i! anti, 3o
indicates RA, M (memory).

Claims (1)

[Claims] In a system in which a plurality of terminals are commonly connected to a central processing unit and data is transmitted between each terminal and the central processing unit, the central processing unit includes a terminal used for data processing. A memory including a storage area for identification, in which the storage area for each terminal identification is addressed by multiple digit 7-trace data consisting of upper and lower digits, and the address specified by the -h digit is determined as an absolute address; and an absolute address deriving means for deriving the target address absolute address 7. The absolute address is the first address specified by some number of bits.
and a second absolute address specified by the number of remaining bits.
a setting means for fixedly deriving the absolute address of the memory; and a conversion means for deriving the second absolute address using the remaining number of bits based on a code generated by an interrupt from each of the terminals. Designated device.