JPS58101461A - Gate turn-off thyristor - Google Patents

Abstract

PURPOSE:To improve the gate sensitivity at the turning OFF time without decrease of the turning OFF gain by containing a transistor which amplifies the gate current. CONSTITUTION:An auxiliary transistor II is formed as prescribed around main SCR partsIa,Ib. Electrodes G and K are forwardly biased therebetween at the firing time, and when the sheet resistance R of the PB layer is increased, a gate current flows mainly in the path of the G, an electrode 21, a PB, nE1, electrode 22, PB, nE2, an electrode 1 and the K, the transistor II is driven, and the main SCRsIa,Ib are fired by the amplified (hFE) gate current. Accordingly, the gate current may be 1/hFE of the conventional one. The electrodes G and K are reversely biased therebetween at the arc extinguishing time, carrier is exhausted in the path of the PB, the electrode 22, the external diode D and the G, thereby firing theIa,Ib, and since no current flows from the PB to the nE1, the II is interrupted due to the exhaust of the carrier in the path of the PB and the electrode 21. Since the II may have extremely small capacity as compared with theIa,Ib, the gate current which interrupts the II may be slight. In this manner, the gate sensitivity at the firing time can be remarkably improved without almost altering the turn-OFF gain.

Description

[Detailed Description of the Invention] This invention provides a gate turn-off transistor (hereinafter referred to as "G
It's called TOJ. ).

Figure #I1 is a schematic cross-sectional view showing the structure of the conventional Goo.
E is an n-type emitter jet region, pB is a p-type base region, nB is an n-type base region, 8 is a p-type emitter region, nB is a low resistance n-type space region, and the following are the n111 layer, the pB layer, and the pB layer, respectively.
nB shield e pE141%” 154 Tokof.+11
1! Cathode electrode, (2) gate llam, (3)
is the anode electrode, Jl is the junction between the 91st layer and the nB layer, J,
is the junction between the n1 layer and the pmtm threshold, J3 is the junction between the pB layer and the n1 layer, G is the external gate terminal, K is the external cathode terminal,
The electron beam is the external anode electron. Note that the arrows to the right of the center in the figure indicate the flow of holes and electrons during turn-on, and the arrows to the left of the center indicate the flow of holes and electrons during turn-off, with solid lines corresponding to holes and broken lines corresponding to electrons.

Now, in this GTO, at turn-on, the gate G
- by forward biasing the cathode between the external gate terminal G - the gate electrode [2] - the pB layer - the junction J5 - the n1 layer - the cathode electrode (11 - the external cathode), thereby allowing the gate current to pass through the path to the external cathode electrons , electrons are injected from the 0g layer to the h layer, and further reach the nB+ layer-p]i1 layer, causing hole injection from the pE layer to the n1 layer.This hole reaches the pB layer-nz layer. This promotes injection of electrons from the nx layer to the pb layer.

In this way, τGTO is turned on.

Next, at turn-off, by applying a reverse bias between the gate G and the cathode X, carriers in the pB layer are directly discharged to the gate electrode (2), and injection of electrons from the 81st layer is stopped. In this way, the GTO is turned off.

As mentioned above, the GTO can be turned on and turned off with only a gate signal, so there is no need for a commutation circuit for turn-off as in the case of general Cyrisk, which makes the device smaller, lighter, and less noisy. It is advantageous for However, the turn-off gain of the high power G70 is 3 layers and 5 degrees,
Therefore, a gate reverse current of 3 to 5 V or more is required for the main current, and a much larger gate circuit is required than in the case of normal thyrisk. The advantage of the GTO depends on whether the overall device can be made more compact, taking into account the larger size of the gate circuit and the necessity of the above-mentioned commutation circuit.

During the turn-off period of the GTO, the on-state IIIJ region and the off-state ml111 region coexist, and the off-state region expands from a portion close to the gate electrode (2) to a portion far away.

In other words, at the same time as the energizing chain acid is squeezed, the anode
The cathode voltage increases. Such a process tends to generate hot spots, and to avoid this it is necessary to reduce the impedance between the gate and cathode as much as possible. Therefore, the opposing length of the gate region and cathode region of GTO is much longer than that of a normal thyristor. This means that the gate sensitivity at turn-on is small, and the entire thyristor is Uniform ignition requires a gate forward current several to several tens of times higher than that of a normal thyristor.

Therefore, an important point to take advantage of the advantages of GTO is how to reduce the gate reverse current and gate forward current. However, generally speaking, increasing the gate sensitivity during turn-on tends to reduce the turn-off gain, and it has not been easy to increase both of them.

An object of the present invention is to provide a GTO that can increase gate sensitivity at turn-on without reducing turn-off gain by incorporating a transistor that amplifies gate current.

FIG. 2 is a schematic cross-sectional view showing the structure of an embodiment of the present invention, where Ia and Ib indicate main thyristor portions, and ■ indicates a transistor portion. mail is the emitter chain acid of the transistor part (hereinafter referred to as "auxiliary transistor") ■, (2) is the base electrode of the auxiliary transistor ■, ■ is the emitter electrode of the auxiliary transistor ■ and the gate electrode of the main thyristor Ia + Ib, D is the auxiliary Base electrode 4 of transistor ■ and emitter 0 electrode of auxiliary thyristor ■ and main thyristor Ia, Ib
An external diode, R, connected between the gate electrode 4 of
is the sheet resistance of the h layer directly below the nl1 layer, and J4 is the sheet resistance of the nl1 layer.
This is the junction of the pm layer. Of course, the auxiliary transistor n portion is not provided with a pE layer, and the nB layer is in direct contact with the anode electrode (3).

In this embodiment, at turn-off, by forward biasing between the gate G and the cathode, external gate terminal G-base electrode (2)-p, layer-"ji1 layer-emitter bridge)-pB layer--snow layer - cathode electrode 11 + - path to the external cathode element, and external gate terminal G - base electrode - pB layer - resistor R - to the emitter electrode) - p
The gate electrode is passed along the path of B layer-NZA layer-cathode electrode (1)-external cathode electrons. By increasing the value of the resistor, the current in the former path becomes dominant, and n1
Electrons are injected from the first layer to the pB layer, and the amount of the auxiliary transistor is driven. Then, the gate current amplified by this auxiliary transistor flows from the h layer to the hysteresis layer, and as shown in main thyristor 2b on the right side of the figure, the hayashi is injected from the nh layer to the h layer, and the main thyristor 1. , Ib is turned on. Since the gate current is amplified by the auxiliary transistor ■ and flows into the main sirisk'& Jb, the gate current from the outside is transferred to the auxiliary transistor.Next, at turn-off, by applying a reverse bias between the gate G and the cathode, it is connected to the 91st layer - the auxiliary transistor. The carriers are discharged from the emitter electrode (b) and the gate electrode of the main thyristor (b) through the path of the external diode (coupled to the external gate terminal G) and the main thyristors Ia and ib are turned off. Since no base current is supplied from the pB layer to the nB1 layer of the auxiliary transistor (2), carriers are discharged through the path from the h layer to the space electrode (2) and the transistor is turned off. Since the auxiliary transistor needs to have an extremely small capacitance compared to the main silicon risks xa and 'ib, the gate current required to turn the auxiliary transistor on and off is small. The GTO of this embodiment can be turned off with approximately the same gate current as .

In this way, the gate 11Eft during turn-on can be significantly reduced as described above without increasing the gate 14 flow for turning off the gate 7, so that
Gate control becomes easier and the circuit can be made smaller.

As explained above, in the GTO according to the present invention, the auxiliary engine disk is installed in the inside 'i1. As a result, the gate sensitivity at turn-on can be significantly improved without changing the turn-off gain, and peripheral circuits can be simplified and miniaturized. In particular, this invention is applicable to the C1 pin type GTO and is extremely suitable from both a technical and a manufacturing process standpoint.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic sectional view showing the structure of a conventional GTO, and FIG. 2 is a schematic sectional view showing the structure of a GTO that is an embodiment of the present invention. In the figure, - indicates an n-type base layer (first semiconductor region);
pB is a p-type space layer (second semiconductor region), nB+ is a low resistivity n-type base layer (@3 semiconductor region), and s"ma is an n-type emitter layer (fourth semiconductor region) of the main thyristor section. )
, nil is the n-type emitter layer (sixth semiconductor region) of the auxiliary transistor, pi+ is the p-type emitter layer (sixth semiconductor region), [11&t cathode electrode (first Seiden Tachibana),
@ is the main gate electrode, 4 is the auxiliary gate electrode, (3) is the anode electrode (second main -a+), Ia and Ib are the main iris parts, n4 is the auxiliary transistor part, and D is the diode. In addition, the same reference numerals in the figures indicate corresponding parts.

Claims (2)

[Claims] (1) A #11 semiconductor having a 51i1 conductivity type with high specific resistance, and a second semiconductor having a second conductivity type having a relatively low resistivity, which is provided in contact with one side of this first semiconductor region. #I3 semiconductor region, which is provided in contact with the other semiconductor region of the above-mentioned la1 and has a comparatively low resistivity Broom 1 conductivity type; A semiconductor region of AlI4 of 41 conductivity type M with low resistivity, a main gate in ohmic contact with a part of the surface of the second semiconductor region 5, is formed on a part of the surface of the 61!20 semiconductor region. a fifth semiconductor region having a first conductivity type with low resistivity; formed on the surface of the i@3 semiconductor region at a position opposite to the fourth semiconductor region and having a second conductivity type with low resistivity; @6 semiconductor-castle, the auxiliary gate electrode in ohmic contact with the surface of the 50th semiconductor region and the surface of the 7j42 semiconductor region protruding in the vicinity of the 4th semiconductor region, the #! A raw electrode @l is in ohmic contact with the surface of the semiconductor region of g6. i@3. 1st. The third and first thyristor portions are composed of the second and fourth semiconductor regions, and the third and first thyristor parts. A gate turn-or-thyristor characterized in that an auxiliary transistor section constituted by second and fifth semiconductor regions is formed within the same semiconductor substrate. (2) A patent characterized in that the auxiliary gate electrode is driven from the raw gate electrode via a diode connected in antiparallel to the threshold junction of the 1fI2 semiconductor region and the fifth semiconductor region. A gate turn-off risk according to claim 1.