JPS6152586B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thyristor, particularly a gate turn-off thyristor that is turned on or off by a gate signal.
It concerns thyristors.

Gate turn-off thyristor (hereinafter referred to as
GTO (abbreviated as GTO) has four semiconductor layers of sequentially different conductivity types within a semiconductor substrate, with an anode and a cathode electrode provided on both outermost layers, one adjacent to the outermost layer, and one in between. A gate electrode is provided in the layer. Then, by applying a gate signal that sets the gate electrode at a positive potential between the gate and cathode electrodes, it turns on and transitions from a dessicated state (high resistance state) to a conductive state (low resistance state). By applying a gate signal with a negative potential, it is turned off and transitions from a conductive state to an off state.

The turn-on operation of GTO is gate turn.
It is the same as a normal thyristor without an off function, and a cathode electrode is provided by a gate signal, and a carrier is injected from the outermost layer to the adjacent intermediate layer. It destroys the reverse biased pn junction formed by the other intermediate layer adjacent to the layer, thereby allowing the main current to flow from the anode electrode to the cathode electrode.

The turn-off operation of the GTO is achieved by drawing the main current to the gate electrode by the gate signal, suppressing carrier injection from the outermost layer to the intermediate layer, and from the outermost layer where the anode electrode is provided. On the other hand, it suppresses the injection of carriers into the intermediate layer, thereby restoring the reverse bias state of the pn junction of both intermediate layers and cutting off the main current.

In the turn-off operation of this GTO, the problem is how to properly draw out the main current from the gate electrode. Generally, in order to improve extraction, the outermost layer is formed into a strip, and the gate electrode is provided so as to surround this outermost strip, thereby minimizing the distance between the gate electrode and the outermost strip. On the other hand, if the outermost layer is made into a strip, the current-carrying area will be reduced, so generally a plurality of strip-shaped outermost layers are provided.

On the other hand, if the carrier injection from the outermost layer is suppressed, the turn-off operation will be performed well.
The other intermediate layer is brought into low resistance contact with the anode electrode,
A so-called short emitter structure may be adopted.

On the other hand, the outermost layer is arranged such that when each of the strip-shaped outermost layers is projected onto the anode electrode side, each of the strip-shaped outermost layers exists at least within the projection area,
The direct distance between both outermost layers is reduced, thereby
The forward voltage drop FVD is reduced, and the main current flows evenly through each strip-shaped outermost layer. Therefore, the other outermost layer is divided and provided within the projection area of each strip-shaped outermost layer, taking into account that the turn-off operation can be performed well.

Therefore, a GTO can be viewed as an aggregation of a plurality of GTO units each pairing with each outermost layer in the projection area.

Each semiconductor layer within the semiconductor substrate is formed using well-known impurity diffusion technology and photolithography technology, but from the viewpoint of manufacturing precision, if variations in the structure occur in each GTO unit, it is necessary to・Dispersion appeared in the on and turn-off characteristics, and the main current was concentrated only in a specific GTO unit, which had the disadvantage of easily causing thermal breakdown.

Therefore, an object of the present invention is to provide a thyristor that allows a main current to flow through each GTO unit on average and performs good on/off operations even if manufacturing accuracy is low.

A feature of the present invention that achieves the above object is that each GTO unit was provided individually, but a portion that spans the projection area adjacent to the outermost layer is provided to interconnect adjacent GTO units. It's what I did.

The present invention will be explained below with reference to embodiments shown in the drawings.

FIGS. 1 and 2 show an embodiment of the present invention, and FIG. 1 shows the semiconductor substrate 1 itself, and the electrodes and surface stabilizing protective film are omitted.

In both figures, the semiconductor substrate 1 has n _E layers 2a to 2.
It is composed of c, p _B layer 3, n _B layer 4, p _E layers 5a to 5d, and n ⁺ layers 6 and 7. n _E layer 2a to 2f
has a rectangular shape in the figure, and the p _E layer has a rectangular shape of 5.
It consists of a, 5b and ring-shaped parts 5b, 5c. n _E layer 2
a-2c, p _B layer 3 and n ⁺ layer 6 are exposed on the upper main surface of semiconductor substrate 1, and p _E layers 5a-5d and n ⁺ layer 7 are exposed on the lower main surface. A groove 8 is provided around the upper main surface of the semiconductor substrate 1, and a Pn junction _J2 formed by the _pB layer 3 and the _nB layer 4 is exposed in the groove 8, and the surface is stabilized by a glass 9. has been made into
Planar formed by n _E layers 2a to 2c and p _B layer 3
The surface of the pn junction J ₃ is stabilized by a silicon oxide film 10 provided on the upper main surface.

The cathode electrodes 11a to 11c are n _E layers 2a to 2
The gate electrode 12 is provided in a strip shape on p _B
It is provided on the layer 3 so as to surround the n _E layers 2a to 2c. The n ⁺ layer 7 is a part of the _nB layer 4,
Since the n ⁺ layer 7 is exposed on the lower main surface and the anode electrode 13 is provided on the lower main surface, the planar pn formed by the _nB layer 4, the n ⁺ layer 7 and the _pE layers 5a to 5d. Junction _J1 has a short emitter structure.

Both of the n ⁺ layers 6 and 7 are exposed on the side peripheral surface of the semiconductor substrate 1. When a depletion layer is formed in the pb junction J ₁ or J ₂ due to reverse bias, the n ⁺ layers 6 and 7 act as channel stoppers to stop the elongation of the channel that is connected to this depletion layer and formed on the substrate surface. It fulfills the following.

As shown in FIG. 1, the p _E layers 5b and 5c are located directly under the projection of the n _E layers 2a to 2c, _respectively .
It is provided across the projection areas 2c. Therefore, each layer existing around each n _E layer 2a to 2c
The GTO units are connected on the anode electrode side by _pE layers 5b and 5c.

Next, the turn-on operation will be explained.

When a part of the pn junction J ₃ becomes conductive due to the gate signal, from the n _E layers 2a to 2c in that part,
Electrons are injected into the p _B layer 3. This electron is at the p-n junction
When it reaches the depletion layer formed in the _J2 part, it is pulled down to the _nB layer 4 by the high electric field, thereby destroying the carrier concentration balance between the _nB layer 4 and the _pE layers 5a to 5d. Holes from _E layers 5a to 5d are n _B layer 4
When this hole reaches the depletion layer,
They are attracted to the p _B layer 3 by the high electric field, and as a result, electron injection occurs again from the n _E layers 2a to 2c. By repeating this process, the semiconductor substrate 1 transitions to a conductive state.

Now, suppose that electron injection occurs only from the _nE layer 2c as shown by arrow A in FIG _. 2 due to variations in characteristics.
Injection of holes as shown by arrows B and C also occurs from 2 to 3, and only the GTO unit centered on this _nE layer 2c causes a turn-on operation. However, since the P _E layer 5c also causes hole injection as shown by the arrow D, this hole injection upsets the carrier concentration balance at the pn junction J ₃ between the N _E layer 2b and the P _B layer 3, as shown by the arrow D. As shown by E, electrons are injected from the n _E layer 2b.
In this way, initially n
Even if electron injection does not occur from _{the E} layer, other
Induced by the turn-on action of the GTO unit, p _E
Each GTO unit connected by the layer all undergoes a turn-on operation, and all GTO units transition to a conductive state, completing the turn-on operation.

Therefore, the current does not flow concentrated in some GTO units, and the semiconductor substrate 1 does not suffer thermal breakdown.

Here, the fact that the _pE layers 5a and 5d exist without spanning other GTO units will be explained.

Each of the strip-shaped _nE layers 2a to 2c has a width of approximately 200 μm in consideration of current extraction at turn-off.
It is common to set it at the m position. Therefore, for example, the distance ₁ between p _E layers 5a and 5b is n _E layers 2a to 2
The width is less than the width of c, for example, about 150 μm.

On the other hand, the width of the gate electrode 12 between the n _E layers 2a to 2c is designed to be as wide as possible in order to reduce the electrical resistance within the electrode 12. Therefore, the inner diameter ₂ of the annular p _E layers 5b and 5c becomes large, and is about 210 μm, for example.

Here, by designing the hole diffusion length L in the n _B layer 4 to be approximately 190 μm,
When L< ₁ , the holes injected into the _pE layers 5a and 5b, 5c and 5d influence each other,
For example, the injection of electrons shown by arrow A is caused by arrows B and C.
The injection of holes shown by is caused to occur.

Therefore, there is some structural difference between the GTO unit centered on the _nE layer 2b existing inside and the GTO unit centered on the _nE layers 2a and 2c existing at the edges due to the difference in the shape of the _pE layer. Even if there is a difference, the injection of holes and electrons is almost balanced, and the main current flows through each GTO unit on average. When a current flows through the semiconductor substrate 1 and the temperature rises, the hole diffusion length L becomes longer than at room temperature, so there is no change in the main current flow area compared to room temperature. Does not occur.

In each GTO unit, n _E layers 2a to 2c, p
A four-layer thyristor region consisting of _B layer 3, n _B layer 4 and p _E layers 5a to 5d and a three layer region of npn transistor consisting of n _E layers 2a to 2c, p _B layer 3 and n _B layer 4 are combined. It has a unique structure.

When the thyristor region is in a conductive state, the current flowing through the thyristor region serves as the base current of the transistor region, so that a current also flows through the transistor region. Therefore, a main current flows throughout the semiconductor body 1.

Next, the turn-off operation will be explained.

The main current is transferred to the gate electrode 12 by the gate signal.
Pull it out. That is, when holes are extracted, electron injection from each n _E layer 2a to 2c also decreases. Therefore, the number of holes injected from each _pE layer 5a to 5d decreases, and eventually the hole injection from each _pE layer 5a to 5d stops, so each pn junction J ₁ to _{J 3} Recovers the blocked state.

Now, due to variations in characteristics, holes are extracted around the n _E layer 2c well, and the n _E layer 2a,
It is assumed that holes are not drawn out well around 2b.

At this time, as the injection of electrons shown by arrow A in the n _E layer 2c decreases, the injection of holes shown by arrows B and C from the p _E layers 5c and 5d correspondingly decreases as well. Since the entire _pE layer 5c is at the same potential,
The amount of holes injected indicated by arrow D decreases in the same manner as the decrease in holes indicated by arrow C. Since the injection of holes indicated by arrow D also causes the injection of electrons indicated by arrow E, a decrease in the injection of holes indicated by arrow D induces a decrease in injection of electrons indicated by arrow E.

As described above, the injection of holes and electrons rapidly decreases due to the chain, and even if there are variations in the characteristics of each GTO unit, each GTO unit causes a turn-off operation, and all GTO units turn off. The unit turns off and enters the wean state.

In each GTO unit, if the thyristor 4-layer region becomes inactive, the transistor 3-layer region also becomes
Since there is no base current, it becomes a weeping state. In this case, as the current in the thyristor region decreases, the current in the three-layer transistor region also decreases.

In the above embodiment, all the GTO units are connected by the _pE layers 5b and 5c, but it is not necessary to connect all the GTO units by the _pE layer.
The effects of the present invention can be achieved even if only some GTO units whose turn-on or turn-off behavior is slow due to the structure of the semiconductor substrate are connected through the _pE layer.

FIGS. 3 and 4 each show other embodiments of the present invention. In the embodiment of FIG. 3, FIG.
The difference from the embodiment shown in FIG. 2 is that the central p _E layer 5
b and 5c are not ring-shaped but U-shaped.

This embodiment is effective when the number of gate leads attached to the gate electrode is limited due to the chip size of the semiconductor substrate 1.

In GTO, the farther away from the gate lead the further the current is drawn, the more the current tends to concentrate there.

Even if the gate lead must be attached at the location indicated by the dashed line in the figure, the p _E layers 5b, 5
If c is open, no holes are injected in this part, so there is no turn/turn in this part.
There is no concentration of current when the device is off.

In the embodiment of FIG. 4, the _pE layers are not divided, but are all connected.

p Since there are many connection points in _{the E} layer 5, Figs. 1 and 2
The increase or decrease of electron and hole injection during turn-on or turn-off is faster and transferred to other GTO units than in the embodiment shown in the figure.
Turn-on and turn-off times are reduced. Furthermore, since the area of the _pE layer 5 also increases, the area of the four-layer thyristor region increases, which has the effect of increasing the amount of main current flowing accordingly.

Although the above embodiments have been described using a rectangular semiconductor substrate as an example, the present invention can also be implemented with a circular semiconductor substrate. In that case, the _nE layer and the _pE layer may be arranged radially.

Further, the gate may adopt a widening gate structure or the like.

The semiconductor substrate 1 can be manufactured without adding lifetime killers such as gold by appropriately selecting the short circuit resistance determined by the shapes of the _nE and _pE layers, the thickness of each semiconductor layer, and the impurity concentration. Although it is possible to perform a turn-off operation (for details, please refer to Japanese Patent Application No. 18484/1984 filed by the same applicant), the present invention does not prevent the reverse operation even if a lifetime killer is added. It can be applied even if you are not present.

[Brief explanation of the drawing]

1 and 2 show one embodiment of the present invention, in which FIG. 1 is a plan view of the cathode side of the semiconductor substrate, FIG. 2 is a cross-sectional view taken along the - cutting line of FIG. 1 and 4 are plan views of a semiconductor substrate on the cathode side, respectively, showing other embodiments of the present invention. 1...Semiconductor substrate, 2a-2c...n _E layer, 3
...p _E layer, 4...n _B layer, 5,5a-5d...p
_E layer, 6, 7... n ⁺ layer, 8... groove, 9, 10...
Surface stabilizing film, 11a to 11c... cathode electrode, 12... gate electrode, 13... anode electrode.

Claims (1)

[Scope of Claims] 1. A semiconductor substrate having four semiconductor layers having successively different conductivity types, one outermost layer being divided into a plurality of layers, each outermost layer of the one being provided with a cathode electrode, One intermediate layer adjacent to each outermost layer of the one above is provided with a gate electrode so as to surround each outermost layer of one of the above, and the other outermost layer and the other intermediate layer adjacent to the outermost layer of the other one are provided with a gate electrode so as to surround each outermost layer of the one above. , a thyristor which is exposed on one main surface of a semiconductor substrate, an anode electrode is provided on this main surface, and a part of the other outermost layer is present in a region where each of the outermost layers of one of the above is projected onto the anode electrode side. A thyristor, wherein a part of the other outermost layer has a portion provided over adjacent projection areas of each of the one outermost layers. 2. A thyristor according to claim 1, characterized in that the other outermost layer is divided and provided, and the one provided spanning the projection area of each outermost layer is ring-shaped. 3. The thyristor set forth in claim 1, wherein the other outermost layer is provided separately, and the thyristor provided spanning the projection area of each outermost layer is U-shaped. . 4. The thyristor according to claim 1, wherein each of the outermost layers has a rectangular shape.