JPS58101301A - Back-up system of process controller - Google Patents

Abstract

PURPOSE:To reduce an operation load of a buffer of a main controller, and to simplify the constitution, by immediately storing a data which is always varied, in a back-up memory from the main controller, and storing other data only when it has been varied. CONSTITUTION:In a CPUm, a data check is executed, and if its data is an ''always varied data'', it is transferred to a buffer BFm, and thereafter, is sent out to a switching device CG, therefore, a CPUc stores a data related to a memory MMc. Unless said data is an ''always varied data'', it is transferred to the buffer when the CPUm has decided that there is a variation, is stored in the memory, and when there is no variation, transfer to the buffer and store to the memory are not executed. The quantity of a data which is always varied is much smaller than that of a data which is not always varied, the quantity of a data which must be processed simultaneously is reduced remarkably, and a constitution scale of the BFm can be simplified freely.

Description

DETAILED DESCRIPTION OF THE INVENTION The main controller that performs process control, the sub-controller that performs process control on behalf of the main controller due to a failure, and the relationship between The present invention relates to a backup system in a process control device, which is comprised of a switching device having a backup interface and a backup switch.

Fig. 1 is a four-wheel diagram showing an example of such a process control device, in which a p1 main controller MCT and a sub-controller SCT are provided, and a switch CG is provided as an intermediate between them. , the main controller MCT, the Oka controller 8CT, and the switch CG each include a processor CPUmS, CPU5, CPUe, such as a microphone processor, and a memory MMm for storing data.

MMs and MMe are separated, and the processor CPUm of the main controller MCT executes process control while accessing data to the memory MMm.

Furthermore, when a failure occurs in the main controller MCT, the processor CPU5 of the sub-controller 8CT starts operating according to a command via the switch CGt, and similarly to the main controller MCT, accesses data to the memory MM1. However, for multiple main controllers MCT,
Only one sub-controller 8CT is provided, and the switch CG processor 9 is provided in correspondence with the main controller. MM@ where the CPU 5 is constantly operating and receives each data sent from the main controller MCT via the buffer BFm.
The contents of the memory MMe are sequentially stored in the main control [SMCT] and are stored in the memory MMII of the subcontroller SCT in response to a fault in the SMCT.
It is to be transferred to.

Therefore, the contents of the memory MMm always match the contents of the memory MMe, and the contents of the memory h/Me are transferred to the memory MMm via the buffer BFs as necessary, so that the processor If a failure occurs in the main controller MCT, the CPU- can take over control of the main controller MCT.

However, in the past, all data in the main controller MCT was transferred to the memory MMc via the buffer BFm. The amount of data that can be handled must be increased, and the structure of the buffer BFm using registers and the like becomes large-scale, resulting in a drawback that the device cost becomes high.

The purpose of the present invention is to fundamentally solve such drawbacks of the conventional technology, and while constantly changing data is immediately stored from the main controller to a backup mail, data that does not change constantly is stored in a backup memory. By storing only the colors that have occurred in the backup memory, the buffer operation load on the main controller is reduced, and the configuration is greatly simplified and highly effective for process control. It provides a backup method for the device.

Hereinafter, the present invention will be explained in detail with reference to the flowchart of FIG. 2 showing an embodiment.

Figures 1 and 2 show the operational status of data transfer and data storage by the processors CPUm and CPU of the main controller MCT and the switch CG.
Ura lfc Oi Te 1. Perform a data check
This is 1 constantly changing data! If 10 is YES, the data is immediately transferred to the note buffer, and in order to send the data to the switch CG, the data is stored in the memory MMaK by the processor CPU@5j%store in memory'.

On the other hand, 1 constant expense data! In NO of l,
There is one change in processor CPUm! Write down I's judgment,
If this is YES, a transfer I is made to 1 buffer,
1 memory is stored, but if ``change ↑l'' is NO, the process immediately returns to the beginning and the turtle buffer transfer 1 is performed.
11 Storage I to memory is not performed.

Note that the data that constantly changes is the change cycle of process quantities, and the data that does not constantly change are parameters of control calculations, etc., and include changes in commands from the upper control device, and artificial changes in set values. etc., the amount of constantly changing data is extremely small compared to the constantly changing data i, and according to the method shown in Figure 2, the amount of data that must be simultaneously handled by the buffer BFm is greatly reduced. do.

Therefore, the configuration size of the buffer BFm can be simplified, the device cost can be significantly reduced, and the time devoted to data transfer can be extremely reduced.

Main controller MCT and backup memo 11
Any device equipped with MM@ can be applied regardless of the presence or absence of the sub-controller 8CT and the switch CG, and the configuration of the device can be modified in various ways depending on the conditions.

As is clear from the above description, according to the present invention, the structure of the buffer that mediates between the main controller and the backup memory is greatly simplified, the cost of the device can be reduced, and the data transfer The time required for processing is greatly reduced, the operating load on the processor is reduced, and significant effects can be obtained in various process control devices.

[Brief explanation of drawings]

FIG. 91 is a block diagram showing an example of the configuration of the apparatus, and FIG. 2 is a flow chart showing an embodiment of the present invention. MCT...Main controller, 8CT...Sub controller,
CG...Switcher, CPUm, CPILa. CPUc...processor, MMm, MMs, h
/Me...Memory, BFm, BFs...
buffer. Patent applicant Yamatake Honeywell Co., Ltd. Agent Masaki Yamakawa (and 1 other person) 1 @ Figure 2 Continued from page 1 0 Inventor Yasuo Tomita 4-28-1 Nishirokugo, Ota-ku, Tokyo Yamatake Honeywell Co., Ltd. Inventor: Atsushi Makai Yamatake Honeywell Co., Ltd., 4-28-1 Nishirokugo, Ota-ku, Tokyo Inventor: Toru Abe Yamatake Honeywell Co., Ltd., 4-28-1 Nishirokugo, Ota-ku, Tokyo Company Kamadamaba q

Claims (1)

[Claims] In a process control device that includes a main controller and a backup memory for storing future data, data that constantly changes is stored from the main controller to the memory, and data that does not constantly change is stored in the memory when it changes. A backup method for process control equipment that only stores data from the main controller to the memory.