JPS5794979A - Bubble memory tester - Google Patents

Abstract

PURPOSE:To set an optional pulse for some cycle by determining the leading and trailing edges of a prescribed pulse selected in two pulse sequences which synchronize with bubble memory cycles and with intermediate points of them. CONSTITUTION:A pulse sequence generating circuit 3a generates a pulse sequence which synchronizes with bubble memory cycles, and a pulse sequence generating circuit 3b generates a pulse sequence which synchronizes with intermediate points of the bubble memory cycles. Those pulse sequences are input- ted to a pulse leading-edge selecting circuit 4 and a pulse trailing-edge select- ing circuit 5 respectively to select pulses in each pulse sequence with a selection signal from a control circuit 6. The pulse outputted from the circuit 4 and determining a leading edge is ANDed with a pulse GR, outputted from an operation range control circuit 8 and determining operation range, through an AND gate G, whose output is inputted to the set terminal of an FF7. On the other hand, the pulse outputted by the circuit 5 and determining a trailing edge is inputted, as it is, to the reset terminal of the FF7 to output a desired pulse from its output terminal Q.