JPS5794864A - Data process system - Google Patents

Data process system

Info

Publication number
JPS5794864A
JPS5794864A JP16958880A JP16958880A JPS5794864A JP S5794864 A JPS5794864 A JP S5794864A JP 16958880 A JP16958880 A JP 16958880A JP 16958880 A JP16958880 A JP 16958880A JP S5794864 A JPS5794864 A JP S5794864A
Authority
JP
Japan
Prior art keywords
data
storage device
main storage
ssm13
auxiliary storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16958880A
Other languages
Japanese (ja)
Inventor
Seiji Izumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP16958880A priority Critical patent/JPS5794864A/en
Publication of JPS5794864A publication Critical patent/JPS5794864A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To increase the data processing capacity, by reducing the time during which a data processor exists for the transfer of the data between an auxiliary storage device and a main storage device and at the same time excluding a main storage switch between the data processor and the main storage device. CONSTITUTION:A CPU1 is connected to a main storage device (MS) consisting of banks (MSB) 9 and 10 via data buses 50 and 51. At the same time, the bus 50 is connected to auxiliary storage devices SSM13 and 14 via auxiliary storage switches SSW11 and 12. In the same way, the bus 51 is connected to SSM13 and 14 via SSW11 and 12. The SSM13 and 14 require no data channel device.
JP16958880A 1980-12-03 1980-12-03 Data process system Pending JPS5794864A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16958880A JPS5794864A (en) 1980-12-03 1980-12-03 Data process system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16958880A JPS5794864A (en) 1980-12-03 1980-12-03 Data process system

Publications (1)

Publication Number Publication Date
JPS5794864A true JPS5794864A (en) 1982-06-12

Family

ID=15889261

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16958880A Pending JPS5794864A (en) 1980-12-03 1980-12-03 Data process system

Country Status (1)

Country Link
JP (1) JPS5794864A (en)

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