JPS5792483A - Storage circuit device - Google Patents

Storage circuit device

Info

Publication number
JPS5792483A
JPS5792483A JP55168608A JP16860880A JPS5792483A JP S5792483 A JPS5792483 A JP S5792483A JP 55168608 A JP55168608 A JP 55168608A JP 16860880 A JP16860880 A JP 16860880A JP S5792483 A JPS5792483 A JP S5792483A
Authority
JP
Japan
Prior art keywords
lines
assigned
memory cell
circuit device
storage circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55168608A
Other languages
Japanese (ja)
Inventor
Kenichi Nagao
Toshiaki Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55168608A priority Critical patent/JPS5792483A/en
Publication of JPS5792483A publication Critical patent/JPS5792483A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To read memeory cells arranged in a matrix simultaneously by selecting one of two data lines, assigned by two selection lines assigned to every memory cell, correspondingly. CONSTITUTION:To each memory cell 10 in a matrix array, two selection lines COL and two data lines BUS are assigned, and the lines COL control selective connections between the corresponding lines BUS and the cell 10. This constitution enables data of the memory cell at difference address positions to be read simultaneously, thereby realizing a storage circuit device which is accessible at a high speed.
JP55168608A 1980-11-29 1980-11-29 Storage circuit device Pending JPS5792483A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55168608A JPS5792483A (en) 1980-11-29 1980-11-29 Storage circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55168608A JPS5792483A (en) 1980-11-29 1980-11-29 Storage circuit device

Publications (1)

Publication Number Publication Date
JPS5792483A true JPS5792483A (en) 1982-06-09

Family

ID=15871202

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55168608A Pending JPS5792483A (en) 1980-11-29 1980-11-29 Storage circuit device

Country Status (1)

Country Link
JP (1) JPS5792483A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04111296A (en) * 1990-08-30 1992-04-13 Nippon Steel Corp Semiconductor memory and memory cell

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04111296A (en) * 1990-08-30 1992-04-13 Nippon Steel Corp Semiconductor memory and memory cell

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