JPS5779748A - Packet exchange system - Google Patents
Packet exchange systemInfo
- Publication number
- JPS5779748A JPS5779748A JP55155075A JP15507580A JPS5779748A JP S5779748 A JPS5779748 A JP S5779748A JP 55155075 A JP55155075 A JP 55155075A JP 15507580 A JP15507580 A JP 15507580A JP S5779748 A JPS5779748 A JP S5779748A
- Authority
- JP
- Japan
- Prior art keywords
- line
- data
- memory
- section
- header
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
PURPOSE:To achieve a packet exchange system with high efficiency, by transferring only a prescribed length part including the header of packet to a central processing section. CONSTITUTION:The 2nd memory 7 is provided between a line allocation section 1 and a central processing section 6. An input data from the line is assembled to a character at a line corresponding circuit 11 and stored on a line buffer memory 13. When the data reaches a prescribed transfer unit, it is transferred to the central processing section 6 via a transfer circuit from a control circuit 2, the control circuit 2 counts the number of transferred characters and when it counts a prescribed length including the header of the packet, the data on and after is transferred to the 2nd memory 7. When the section 6 processes the header and determines it with a transmission line, the said data is returned to the control circuit 2, where it transfers the line buffer memory 13 and accesses the 2nd memory 7 and transfers the remaining data. Thus, the efficiency of the section 6 can be increased the delay in transfer can be reduced.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55155075A JPS5779748A (en) | 1980-11-04 | 1980-11-04 | Packet exchange system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55155075A JPS5779748A (en) | 1980-11-04 | 1980-11-04 | Packet exchange system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5779748A true JPS5779748A (en) | 1982-05-19 |
Family
ID=15598100
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55155075A Pending JPS5779748A (en) | 1980-11-04 | 1980-11-04 | Packet exchange system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5779748A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5571339A (en) * | 1978-11-22 | 1980-05-29 | Fujitsu Ltd | Packet transfer circuit system |
-
1980
- 1980-11-04 JP JP55155075A patent/JPS5779748A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5571339A (en) * | 1978-11-22 | 1980-05-29 | Fujitsu Ltd | Packet transfer circuit system |
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