JPS6482251A - Transfer device - Google Patents

Transfer device

Info

Publication number
JPS6482251A
JPS6482251A JP62242129A JP24212987A JPS6482251A JP S6482251 A JPS6482251 A JP S6482251A JP 62242129 A JP62242129 A JP 62242129A JP 24212987 A JP24212987 A JP 24212987A JP S6482251 A JPS6482251 A JP S6482251A
Authority
JP
Japan
Prior art keywords
inputted
packets
plural
input
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62242129A
Other languages
Japanese (ja)
Inventor
Masahiko Koike
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62242129A priority Critical patent/JPS6482251A/en
Publication of JPS6482251A publication Critical patent/JPS6482251A/en
Pending legal-status Critical Current

Links

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  • Multi Processors (AREA)
  • Computer And Data Communications (AREA)

Abstract

PURPOSE:To efficiently perform the communication among respective processors of plural transfer devices by providing input buffers in which packets inputted to plural input ports are temporarily stored, connection memories, and control circuits. CONSTITUTION:Packets inputted to input ports 10 and 20 of plural transfer devices are inputted to packet buffers 101 and 102 as input buffers, and bit strings 12 and 22 of a part of them are supplied to connection memories 111 and 112. Memories 111 and 112 output codes 13 and 23 indicating output ports to which inputted packets should be outputted, and control circuits 121 and 122 transfer data 11 or 21 of inputted packets to a corresponding output port 30 or 40 in accordance with values of input codes 13 and 23. Output circuits 131 and 132 receive packet transfer requests 14 and 24 or 15 and 25 from circuits 121 and 122 and arbitrate the contention to transmit packets from output ports 30 and 40. Transfer devices are connected in many stages between processors to efficiently perform the communication among plural processors.
JP62242129A 1987-09-25 1987-09-25 Transfer device Pending JPS6482251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62242129A JPS6482251A (en) 1987-09-25 1987-09-25 Transfer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62242129A JPS6482251A (en) 1987-09-25 1987-09-25 Transfer device

Publications (1)

Publication Number Publication Date
JPS6482251A true JPS6482251A (en) 1989-03-28

Family

ID=17084736

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62242129A Pending JPS6482251A (en) 1987-09-25 1987-09-25 Transfer device

Country Status (1)

Country Link
JP (1) JPS6482251A (en)

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