JPS5779545A - Communication controller - Google Patents
Communication controllerInfo
- Publication number
- JPS5779545A JPS5779545A JP55153607A JP15360780A JPS5779545A JP S5779545 A JPS5779545 A JP S5779545A JP 55153607 A JP55153607 A JP 55153607A JP 15360780 A JP15360780 A JP 15360780A JP S5779545 A JPS5779545 A JP S5779545A
- Authority
- JP
- Japan
- Prior art keywords
- interruption
- register
- address
- control
- host device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
Abstract
PURPOSE:To reduce a load on a host device by generating an address on the basis of a received character and a reception state, by reading a prepared control word by the address, and by performing an interruption or transfer to the host device. CONSTITUTION:One received character stored in a receiving buffer register 5 through a signal line group 112 is compared with the contents of a transmission control code register 1 by a comparing circuit 2, and the value of an address register 3 for a transmission control code storage is increased one by one, until coincidence is attained. A control word in a control-word storage register 7, on the other hand, consists of a bit group B0, a bit B1, and a bit group B2, and is read out by an address generated by a control word storage address generating circuit 4, i.e., the outputs of the registers 6 and 3. The B0 of the control word is stored in the register 6, and the B1 and B2 are supplied to an interruption control circuit 8. If, however, the B1 is a 1, an interruption request is sent to a host device and the B2 is transferred as an interruption factor through output line groups 110 and 111, thereby inhibiting an interruption when the B1 is a 0.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55153607A JPS5779545A (en) | 1980-10-31 | 1980-10-31 | Communication controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55153607A JPS5779545A (en) | 1980-10-31 | 1980-10-31 | Communication controller |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5779545A true JPS5779545A (en) | 1982-05-18 |
JPS6141430B2 JPS6141430B2 (en) | 1986-09-16 |
Family
ID=15566175
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55153607A Granted JPS5779545A (en) | 1980-10-31 | 1980-10-31 | Communication controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5779545A (en) |
-
1980
- 1980-10-31 JP JP55153607A patent/JPS5779545A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6141430B2 (en) | 1986-09-16 |
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