JPS577633A - Ttl circuit - Google Patents

Ttl circuit

Info

Publication number
JPS577633A
JPS577633A JP8117680A JP8117680A JPS577633A JP S577633 A JPS577633 A JP S577633A JP 8117680 A JP8117680 A JP 8117680A JP 8117680 A JP8117680 A JP 8117680A JP S577633 A JPS577633 A JP S577633A
Authority
JP
Japan
Prior art keywords
vbe1
buffer
clamping
output
ttl circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8117680A
Other languages
Japanese (ja)
Inventor
Terumasa Fukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8117680A priority Critical patent/JPS577633A/en
Publication of JPS577633A publication Critical patent/JPS577633A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01Modifications for accelerating switching
    • H03K19/013Modifications for accelerating switching in bipolar transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To speed the operation of a TTL circuit and to reduce its power consumption by shortening a propagation delay time by lowering the high level of the TTL circuit. CONSTITUTION:When a low-level signal is applied to at least either one of input terminals 11 and 12, a phase-division transistor TR22 and an output TR25 both turn off. The collector potential of the phase TR22 is elevated by a resistance 2 and off buffer TRs23 and 24 turn on to drive a load, elevating an output voltage. The emitter potential of the off buffer TR23 is clamped by a clamping circuit consisting of resistances 6 and 7 and a clamping TR26 to [(R6+R7)/R7].VBE1 (where R6 and R7 are resistance values of the resistances 6 and 7 and VBE1 is the base-emitter voltage of the clamping TR) and does not rise any more. Then, the output high level is [(R6+R7)/R7].VBE1-VBE2 (where VBE2 is the base-emitter voltage of the off buffer TR).
JP8117680A 1980-06-16 1980-06-16 Ttl circuit Pending JPS577633A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8117680A JPS577633A (en) 1980-06-16 1980-06-16 Ttl circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8117680A JPS577633A (en) 1980-06-16 1980-06-16 Ttl circuit

Publications (1)

Publication Number Publication Date
JPS577633A true JPS577633A (en) 1982-01-14

Family

ID=13739150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8117680A Pending JPS577633A (en) 1980-06-16 1980-06-16 Ttl circuit

Country Status (1)

Country Link
JP (1) JPS577633A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61290820A (en) * 1985-06-19 1986-12-20 Hitachi Micro Comput Eng Ltd Logic circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61290820A (en) * 1985-06-19 1986-12-20 Hitachi Micro Comput Eng Ltd Logic circuit

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