JPS5773574A - Sample clock generator - Google Patents

Sample clock generator

Info

Publication number
JPS5773574A
JPS5773574A JP14829980A JP14829980A JPS5773574A JP S5773574 A JPS5773574 A JP S5773574A JP 14829980 A JP14829980 A JP 14829980A JP 14829980 A JP14829980 A JP 14829980A JP S5773574 A JPS5773574 A JP S5773574A
Authority
JP
Japan
Prior art keywords
synchronizing signal
synchronizing
output
vertical
phase comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14829980A
Other languages
Japanese (ja)
Inventor
Kenji Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP14829980A priority Critical patent/JPS5773574A/en
Publication of JPS5773574A publication Critical patent/JPS5773574A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)

Abstract

PURPOSE:To enable correspondence to television signals automatically different from synchronizing signal forms, by adopting a PLL with broad dynamic range and stopping the comparison of phase if no hrizontal synchronizing signal is present in the vertical synchronizing period. CONSTITUTION:When a synchronizing signal where no horizotal synchronizing signal exists at vertical synchronizing period is applied to a composite synchronizing signal input terminal 4, the output of an AND circuit 8 is absent, the output of a triggrable multivibrator 11 is inverted to be binary ''1'', and a vertical gate signal 13 of negative polarity is obtained at the output of a vertical synchronizing gate circuit 12. A reference gate circuit 14 blocks horizontal synchronizing signals, and a reproduction synchronzing gate circuit 15 blocks a reproduction synchronizing signal 16 and they are applied to a phase comparator 17. The output of the phase comparator 17 is applied to a voltage controlled oscillator 19 via a low pass filter 18. When a composite synchronizing signal is applied to an input terminal 4, the horizontal synchronizing signal 10 and the reproducing synchronizing signal 16 are applied to the phase comparator 17.
JP14829980A 1980-10-24 1980-10-24 Sample clock generator Pending JPS5773574A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14829980A JPS5773574A (en) 1980-10-24 1980-10-24 Sample clock generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14829980A JPS5773574A (en) 1980-10-24 1980-10-24 Sample clock generator

Publications (1)

Publication Number Publication Date
JPS5773574A true JPS5773574A (en) 1982-05-08

Family

ID=15449667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14829980A Pending JPS5773574A (en) 1980-10-24 1980-10-24 Sample clock generator

Country Status (1)

Country Link
JP (1) JPS5773574A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0218406A2 (en) * 1985-10-01 1987-04-15 Seiko Instruments Inc. Sampling clock generation circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0218406A2 (en) * 1985-10-01 1987-04-15 Seiko Instruments Inc. Sampling clock generation circuit

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