JPS5769752A - Semiconductor mounting structure for substrate for electronic timepiece - Google Patents
Semiconductor mounting structure for substrate for electronic timepieceInfo
- Publication number
- JPS5769752A JPS5769752A JP55144306A JP14430680A JPS5769752A JP S5769752 A JPS5769752 A JP S5769752A JP 55144306 A JP55144306 A JP 55144306A JP 14430680 A JP14430680 A JP 14430680A JP S5769752 A JPS5769752 A JP S5769752A
- Authority
- JP
- Japan
- Prior art keywords
- recess
- substrate
- corner
- mounting structure
- conductive pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
Abstract
PURPOSE:To facilitate the mounting of an electronic wrist timepiece in a limited space by increasing the mounting density by reducing the amounting volume of an IC. CONSTITUTION:An IC containing recess 2 is formed in an insulating circuit substrate 1, and an IC3 is bonded to a conductive pattern in the recess. The stepwise wall surface 5 of the recess 2 is inclined to expand the bottom surface of the recess 2 to be readily form a conductive pattern. The surface 5 may be utilized also as a hole for inlet and gas vent at the time of molding with resin. The planar positioning of the IC3 is positioned by coinciding the corner 6 of the recess 2 with the corner of the IC. Reference numeral 7 represents the height positioning unit of an IC to mount the bonding height of the IC as a base formed horizontally on the bottom of the recess 2 constantly.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55144306A JPS5769752A (en) | 1980-10-17 | 1980-10-17 | Semiconductor mounting structure for substrate for electronic timepiece |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55144306A JPS5769752A (en) | 1980-10-17 | 1980-10-17 | Semiconductor mounting structure for substrate for electronic timepiece |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5769752A true JPS5769752A (en) | 1982-04-28 |
Family
ID=15359005
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55144306A Pending JPS5769752A (en) | 1980-10-17 | 1980-10-17 | Semiconductor mounting structure for substrate for electronic timepiece |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5769752A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6163246B1 (en) * | 2016-12-06 | 2017-07-12 | 西村陶業株式会社 | Manufacturing method of ceramic substrate |
-
1980
- 1980-10-17 JP JP55144306A patent/JPS5769752A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6163246B1 (en) * | 2016-12-06 | 2017-07-12 | 西村陶業株式会社 | Manufacturing method of ceramic substrate |
| JP2018093100A (en) * | 2016-12-06 | 2018-06-14 | 西村陶業株式会社 | Ceramic substrate manufacturing method |
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