JPS576918A - Clock control circuit - Google Patents

Abstract

PURPOSE:To eliminate a storage of an inaccurate data which is caused by a phase clock of the double-phase clocks due to a clock control, by providing a double-phase clock generating circuit, a specific storage means and a circuit that controls the 2nd clock by the output of the storage means. CONSTITUTION:When a clock generating circuit 2 that generates the double-phase clocks of the 1st and 2nd clocks 210 and 220 and a storage control signal 110 are energized, an optional information is stored by the clock 210 and the information is reversed by the rear edge of the clock 220 through a storage means 4. Furthermore control circuits 6 and 8 control the clock 220 with the output of the means 4. For instance, a gate circuit 41 and an FF circuit 42 are used for the means 4, and a delaying circuit 6 and a gate circuit 8 are used for the above-mentioned control circuit to constitute a clock control circuit 1 as shown in the diagram. This circuit 1 controls the storing actions of registers 3 and 7 of a data processing circuit.