JPS5766517A - Pll circuit of pcm processor - Google Patents

Pll circuit of pcm processor

Info

Publication number
JPS5766517A
JPS5766517A JP55141563A JP14156380A JPS5766517A JP S5766517 A JPS5766517 A JP S5766517A JP 55141563 A JP55141563 A JP 55141563A JP 14156380 A JP14156380 A JP 14156380A JP S5766517 A JPS5766517 A JP S5766517A
Authority
JP
Japan
Prior art keywords
signal
pll circuit
master clock
pcm
reproduction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55141563A
Other languages
Japanese (ja)
Inventor
Yukihiko Haikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ARUPAIN KK
Alpine Electronics Inc
Original Assignee
ARUPAIN KK
Alpine Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ARUPAIN KK, Alpine Electronics Inc filed Critical ARUPAIN KK
Priority to JP55141563A priority Critical patent/JPS5766517A/en
Publication of JPS5766517A publication Critical patent/JPS5766517A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10527—Audio or video recording; Data buffering arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To obtain a master clock in a short time even at the beginning of reproduction, etc., by decreasing the time constant of a low-pass filter when an error is detected in a PCM signal, as compared with that when no error is detected in the PCM signal. CONSTITUTION:Right after the power source of a VTR1 is turned on or right after run modes are changed, a reproduced PCM signal generally contains many errors like jitters. Therfore, a CRC check circuit 9 detects the errors and a muting circuit 10 generates a muting signal. As a result, an output is intercepted in an audio signal and a low-pass filter 7 having a small time constant is connected in a PLL circuit. In this case, when a synchronizing signal is obtained from the reproduced signal, the PLL circuit outputs master clock for the synchronizing signal. Thus, a master clock is obtained in a short time in a transient state right after the start of reproduction.
JP55141563A 1980-10-09 1980-10-09 Pll circuit of pcm processor Pending JPS5766517A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55141563A JPS5766517A (en) 1980-10-09 1980-10-09 Pll circuit of pcm processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55141563A JPS5766517A (en) 1980-10-09 1980-10-09 Pll circuit of pcm processor

Publications (1)

Publication Number Publication Date
JPS5766517A true JPS5766517A (en) 1982-04-22

Family

ID=15294876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55141563A Pending JPS5766517A (en) 1980-10-09 1980-10-09 Pll circuit of pcm processor

Country Status (1)

Country Link
JP (1) JPS5766517A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60236167A (en) * 1984-05-09 1985-11-22 Matsushita Electric Ind Co Ltd Clock extracting circuit
JPS62236236A (en) * 1986-04-08 1987-10-16 Sony Corp Time constant change-over circuit for pll
JPH01109838A (en) * 1987-10-23 1989-04-26 Nec Corp De-stack system jitter suppressing circuit
JPH01119128A (en) * 1987-10-31 1989-05-11 Nec Corp Destack system jitter suppressing circuit
JPH021636A (en) * 1987-11-10 1990-01-05 Nec Corp Line switching system
JPH0284453U (en) * 1989-06-07 1990-06-29

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5121711A (en) * 1974-08-19 1976-02-21 Ando Electric

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5121711A (en) * 1974-08-19 1976-02-21 Ando Electric

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60236167A (en) * 1984-05-09 1985-11-22 Matsushita Electric Ind Co Ltd Clock extracting circuit
JPS62236236A (en) * 1986-04-08 1987-10-16 Sony Corp Time constant change-over circuit for pll
JPH01109838A (en) * 1987-10-23 1989-04-26 Nec Corp De-stack system jitter suppressing circuit
JPH01119128A (en) * 1987-10-31 1989-05-11 Nec Corp Destack system jitter suppressing circuit
JPH021636A (en) * 1987-11-10 1990-01-05 Nec Corp Line switching system
JPH0284453U (en) * 1989-06-07 1990-06-29

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