JPS5761354A - Clock regeneration system in spectrum diffusing communication - Google Patents

Clock regeneration system in spectrum diffusing communication

Info

Publication number
JPS5761354A
JPS5761354A JP55136117A JP13611780A JPS5761354A JP S5761354 A JPS5761354 A JP S5761354A JP 55136117 A JP55136117 A JP 55136117A JP 13611780 A JP13611780 A JP 13611780A JP S5761354 A JPS5761354 A JP S5761354A
Authority
JP
Japan
Prior art keywords
inputted
sent
code
clock
correlator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55136117A
Other languages
Japanese (ja)
Other versions
JPS6237857B2 (en
Inventor
Kanehito Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anritsu Corp
Original Assignee
Anritsu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anritsu Corp filed Critical Anritsu Corp
Priority to JP55136117A priority Critical patent/JPS5761354A/en
Publication of JPS5761354A publication Critical patent/JPS5761354A/en
Publication of JPS6237857B2 publication Critical patent/JPS6237857B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/043—Pseudo-noise [PN] codes variable during transmission

Abstract

PURPOSE:To stabilize the operation without deterioration of error ratio of bits, by regenerating a clock by code period sent from a local code generator. CONSTITUTION:Data diffused by a PN code is added to a input terminal 1 and is sent to a correlator 2. Then, codes sent from a local code generator 3 are also supplied to the correlator 2 and regenerated data are inputted to integrator 6 and 7. While, the output sent from the local code generator 3 is inputted to a code detector 4, and the code detector 4 outputs pulses at every a period and inputs to a clock regenerator 5. Integrators 6 and 7 integrate and discharge the regenerated data from the correlator 2 by using clocks C1 and C2 whose phase is slipped by 180 deg.. The outputs of integrators 6 and 7 are inputted to respective adders 8 and 9. The outputs are compared with respective added values by a comparator 10. A clock inputted to a integrator having large output of added value is selected by a gate circuit 11 and is passed.
JP55136117A 1980-09-30 1980-09-30 Clock regeneration system in spectrum diffusing communication Granted JPS5761354A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55136117A JPS5761354A (en) 1980-09-30 1980-09-30 Clock regeneration system in spectrum diffusing communication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55136117A JPS5761354A (en) 1980-09-30 1980-09-30 Clock regeneration system in spectrum diffusing communication

Publications (2)

Publication Number Publication Date
JPS5761354A true JPS5761354A (en) 1982-04-13
JPS6237857B2 JPS6237857B2 (en) 1987-08-14

Family

ID=15167692

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55136117A Granted JPS5761354A (en) 1980-09-30 1980-09-30 Clock regeneration system in spectrum diffusing communication

Country Status (1)

Country Link
JP (1) JPS5761354A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55143863U (en) * 1979-04-05 1980-10-15
JPH01117440A (en) * 1987-10-30 1989-05-10 Kenwood Corp Optimum clock forming device for data receiver

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55143863U (en) * 1979-04-05 1980-10-15
JPH01117440A (en) * 1987-10-30 1989-05-10 Kenwood Corp Optimum clock forming device for data receiver

Also Published As

Publication number Publication date
JPS6237857B2 (en) 1987-08-14

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