JPS6237857B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock recovery method in spread spectrum communication.

Spread spectrum communication has recently been attracting attention as one of the wireless communication methods. This spread spectrum communication method is used in a wide range of fields because it is secure and resistant to jamming interference, it is easy to keep communications secret, and it is also possible to measure distances with high precision using communication radio waves. Ta.

In this type of spread spectrum communication system, when the clock is regenerated when the receiving side receives data spread by a spreading code such as PN (Pseudo Noise) sent from the transmitting side, the clock is regenerated as shown in Figure 1. 1-bit length t of the reproduced data and 1 of the spreading code
If the period T matches, the clock can be obtained from the periodic signal (signal indicating that one period has ended) during the PN generation period.

However, as shown in Figure 2, when the 1-bit length of the reproduced data and the two periods of the spreading code match, it is difficult to determine which of the periodic signals of the spreading code corresponds to the conversion point of the reproduced data. A means of judgment becomes necessary. In other words, it was necessary to determine which of the periodic signals S _A and S _B of the periodic signal shown in FIG.

In this way, when the ratio of the data bit length to the code period is twice or more, a bit synchronization circuit is required to regenerate the clock from the re-issued data, and this bit synchronization circuit is always used at the data conversion point. Therefore, if the number of conversion points is small, synchronization may occur, leading to a decrease in the bit error rate.

This invention was made in view of the above points,
The object of the present invention is to provide a clock regeneration method in spread spectrum communication that enables stable clock regeneration at all times even without a data conversion point.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows the configuration of a receiver according to an embodiment of the present invention. In Figure 3, 1
is an input terminal into which data spread with an NP code is input, 2 is a correlator, 3 is a local code generator, and 4 detects the code from the local code generator 3 and generates a pulse for each period of the code. The generating code detector 5 is a clock regenerator that regenerates a clock according to the period of the pulse from the code detector 4 and outputs first and second clocks C ₁ and C ₂ . Note that in the configuration shown in Fig. 3, the code period is 2 of the data bit length.
The case of double is shown. Therefore, the first and second clocks C ₁ and C ₂ from the clock regenerator 5
are 180° out of phase with each other. 6 is a first clock C that integrates and discharges the reproduced data output from the correlator 2 at the cycle of the _first clock C1.
, 7 is a second integrator that integrates and discharges the reproduced data output from the correlator 2 with the period of the second clock C ₂ , and 8 is the first integrator 6
The first adder 9 adds, for example, 10 to 20 bits of the absolute value of the output of the second integrator 7 just before discharge, and the second adder 9 adds 10 to 20 bits of the absolute value of the output of the second integrator 7 just before discharge. The adder 10 is a comparator that compares the added values of the first and second adders 8 and 9, respectively. A gate circuit 11 selects a clock having the correct phase based on the comparison signal from the comparator 10 and outputs a recovered clock to the clock output terminal 12.

The operation of such a configuration will be explained next. Data spread with the PN code is applied to input terminal 1 and enters correlator 2. At this time, the code from the local code generator 3 is supplied to the correlator 2, and if the phase of this code matches the phase of the code from the transmitting side input to the input terminal 1, the correlator 2 becomes reproduced data (containing noise N) as shown in FIG. 4a, and this reproduced data is input to the first and second integrators 6 and 7.

On the other hand, the output from the local code generator 3 is also input to the code detector 4, and the code detector 4 outputs a pulse as shown in FIG. 4b for each cycle of the code from the local code generator 3. . The output pulses from the code detector 4 are input to the clock regenerator 5, which outputs first and second clocks C ₁ and C ₂ as shown in FIG. 4c and d. In this embodiment, the code period is twice the bit length of the data, so the phases of the first and second clocks C ₁ and C ₂ are
It is shifted by 180°. And the first clock
C ₁ enters the first integrator and the second clock C ₂ enters the second integrator 7. As a result, the reproduced data from the correlator 2 (FIG. 4a) that is input to the first and second integrators 6 and 7 is at the period of the first and second clocks C ₁ and C ₂ . It is integrated and discharged. That is, data is integrated and discharged from the first integrator 6 by the first clock _C1 as shown in FIG. 4e, and data is output from the second integrator 7 by the second clock _C2. It is integrated, discharged, and output as shown in FIG. 4(f). Comparing the outputs of the first and second integrators 6 and 7, the output of the first integrator 6 becomes a large value just before discharge, and the output of the second integrator 7 becomes OV just before discharge. It is nearby. The output of the first integrator 6 is input to the first adder 8, and the output of the second integrator 7 is input to the second adder 9. And the first adder 8
Then, the absolute value of the output of the first integrator 6 just before discharge is
Add 10 to 20 bits and send the added output to comparator 1.
Output to 0. The second adder 9 adds 10 to 20 bits of the absolute value of the output of the second integrator 7 immediately before discharge, and outputs the added output to the comparator 10.

By the way, the above-mentioned addition value of the absolute value becomes a larger value when integrated with a clock that correctly coincides with the data conversion point. Therefore, the comparator 10 compares each of the above added values to determine their magnitude, and the gate circuit 11 selects and passes the clock input to the integrator that outputs the larger added value. in this case,
The first clock _C1 is selected as the correct clock and is output from the gate circuit 11. With this, all that is left is to set this first clock _C1 to a duty of 50%.
All you have to do is format it to the clock. In this way the clock is regenerated.

In the above embodiment, the code period is twice the 1-bit length of the data.
Even in the case of an integer multiple of more than one, the same configuration can be achieved by adding an integrator corresponding to the number.

As explained above, according to the present invention, the clock can be regenerated using the code period from the local code generator, and the regenerated clock is always stable even without data conversion points. Since the bit error rate is not degraded,
In addition, it is possible to provide a clock regeneration system for spread spectrum communication that has various advantages such as not requiring an independent bit synchronization circuit as in the past and thus contributing to stabilization of operation since it does not employ a feedback loop such as a PLL.

[Brief explanation of the drawing]

Figure 1 is a time chart for explaining the clock regeneration operation when 1 bit length of the reproduced data and 1 cycle of the spreading code match, and Figure 2 is a time chart for explaining the clock reproduction operation when 1 bit length of the reproduced data matches 1 cycle of the spreading code. FIG. 3 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 4 is a time chart showing the operation of the same embodiment. DESCRIPTION OF SYMBOLS 1...Input terminal, 2...Correlator, 3...Local code generator, 4...Code detector, 5...Clock regenerator, 6, 7...First and second integrators, 8, 9...
...First and second adders, 10... Comparators, 11...
...Gate circuit.

Claims (1)

[Claims] 1. In the clock recovery method in spread spectrum communication, which receives a signal spread by a spreading code with a period that is an integral multiple of the length of one bit of data and regenerates data and a clock from this signal, the receiving side uses the spreading code. A code synchronized with the code period is generated by a local code generator, and a clock is generated for each period of this code, and the code has a period equal to one bit length of the reproduced data and is of a type equal to an integer multiple of the above integer. A clock is generated, each of these clocks is applied to an integrator provided corresponding to each of these clocks, and the above-mentioned reproduced data is integrated and discharged in synchronization with each clock at the cycle of the clock, and these integrated and discharged data are Desired n bits (n is a positive integer) of the absolute value immediately before discharge of each waveform were added using corresponding adders, and these added values were compared to output the largest added value. 1. A clock regeneration circuit for spread spectrum communication, characterized in that a clock given to an integrator is selected as a re-output clock.