JPS57207457A - Sc bit superimposing system - Google Patents

Sc bit superimposing system

Info

Publication number
JPS57207457A
JPS57207457A JP56092103A JP9210381A JPS57207457A JP S57207457 A JPS57207457 A JP S57207457A JP 56092103 A JP56092103 A JP 56092103A JP 9210381 A JP9210381 A JP 9210381A JP S57207457 A JPS57207457 A JP S57207457A
Authority
JP
Japan
Prior art keywords
bit
circuit
code
signal
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56092103A
Other languages
Japanese (ja)
Inventor
Masayuki Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56092103A priority Critical patent/JPS57207457A/en
Publication of JPS57207457A publication Critical patent/JPS57207457A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
    • H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes

Abstract

PURPOSE:To attain sure superimposition of an SC bit, through the utilization of the advantages of a mBnB code with a simple hardware, by alternately repeating the code conversion of an original signal in m-bit with each word different from parity or using each word twice. CONSTITUTION:A received serial mBnB code is inputted to a serial parallel conversion circuit 1 together with a clock signal in (n/m)f0 frequency to convert the code into a parallel signal in n-bit. The clock (n/m)f0 is frequency-divided by n at a frequency division circuit 4 and the parallel signal in n-bit is inputted to a code converting circuit 2, where the signal is converted into a corresponding parallel signal in m-bit, and each word is converted into a serial original signal in m-bit at a parallel serial conversion circuit 3. To the circuit 3, the clock from the circuit 4 and the clock multiplied by m from a multiplication circuit 7 are applied to control the timing. Thus, the superimposition of SC bits can be attained by utilizing the advantage of the mBnB code through the use of a simple hardware.
JP56092103A 1981-06-17 1981-06-17 Sc bit superimposing system Pending JPS57207457A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56092103A JPS57207457A (en) 1981-06-17 1981-06-17 Sc bit superimposing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56092103A JPS57207457A (en) 1981-06-17 1981-06-17 Sc bit superimposing system

Publications (1)

Publication Number Publication Date
JPS57207457A true JPS57207457A (en) 1982-12-20

Family

ID=14045102

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56092103A Pending JPS57207457A (en) 1981-06-17 1981-06-17 Sc bit superimposing system

Country Status (1)

Country Link
JP (1) JPS57207457A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4682334A (en) * 1984-05-23 1987-07-21 Compagnie Industrielle Des Telecommunications Cit-Alcatel Synchronous data transmission method and device implementing same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4682334A (en) * 1984-05-23 1987-07-21 Compagnie Industrielle Des Telecommunications Cit-Alcatel Synchronous data transmission method and device implementing same

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