JPS5760872A - Vertical-type semiconductor device - Google Patents

Vertical-type semiconductor device

Info

Publication number
JPS5760872A
JPS5760872A JP55137109A JP13710980A JPS5760872A JP S5760872 A JPS5760872 A JP S5760872A JP 55137109 A JP55137109 A JP 55137109A JP 13710980 A JP13710980 A JP 13710980A JP S5760872 A JPS5760872 A JP S5760872A
Authority
JP
Japan
Prior art keywords
layer
type
introduction
silicon layer
amplification factor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55137109A
Other languages
Japanese (ja)
Other versions
JPS6152582B2 (en
Inventor
Katsumi Murase
Akio Tamama
Masahiro Sakagami
Yoshihiko Mizushima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP55137109A priority Critical patent/JPS5760872A/en
Publication of JPS5760872A publication Critical patent/JPS5760872A/en
Publication of JPS6152582B2 publication Critical patent/JPS6152582B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals

Abstract

PURPOSE:To increase an emitter injection efficiency of a current amplification factor by providing a P type amorphous silicon layer including B and Ge on an N type layer of a P type silicon substrate. CONSTITUTION:An amorphous silicon layer 8 containing B and Ge is deposited on an N layer 3 of a P silicon substrate 1 by laying SiH4 in the atmosphere of B and Ge. The maximum concentration of P impurity B which can be included in the amorsphous silicon layer 8 is controlled by solid solubility, limit depends on an amount of distortion created with introduction of other elements. This limit is loosened by introduction of Ge which has a larger ion radius than that of Si, and the maximum concentration of B is largely increased. Further, a hetero junction is formed between layers 3 and 4, so a potential barrier against electrons is higher than a barrier against positive holes. Therefore, an emitter injection efficiency or a current amplification factor is much more increased. Since Ge is inactive, the property of the layer 8 is not deteriorated.
JP55137109A 1980-09-30 1980-09-30 Vertical-type semiconductor device Granted JPS5760872A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55137109A JPS5760872A (en) 1980-09-30 1980-09-30 Vertical-type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55137109A JPS5760872A (en) 1980-09-30 1980-09-30 Vertical-type semiconductor device

Publications (2)

Publication Number Publication Date
JPS5760872A true JPS5760872A (en) 1982-04-13
JPS6152582B2 JPS6152582B2 (en) 1986-11-13

Family

ID=15191046

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55137109A Granted JPS5760872A (en) 1980-09-30 1980-09-30 Vertical-type semiconductor device

Country Status (1)

Country Link
JP (1) JPS5760872A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62279672A (en) * 1986-05-28 1987-12-04 Kanegafuchi Chem Ind Co Ltd Semiconductor device
US5108936A (en) * 1984-10-02 1992-04-28 Interuniveritair Micro Elektronica Centrum Method of producing a bipolar transistor having an amorphous emitter formed by plasma cvd

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5108936A (en) * 1984-10-02 1992-04-28 Interuniveritair Micro Elektronica Centrum Method of producing a bipolar transistor having an amorphous emitter formed by plasma cvd
JPS62279672A (en) * 1986-05-28 1987-12-04 Kanegafuchi Chem Ind Co Ltd Semiconductor device

Also Published As

Publication number Publication date
JPS6152582B2 (en) 1986-11-13

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