JPS5760596A - Parity checking system of control memory - Google Patents

Parity checking system of control memory

Info

Publication number
JPS5760596A
JPS5760596A JP55135528A JP13552880A JPS5760596A JP S5760596 A JPS5760596 A JP S5760596A JP 55135528 A JP55135528 A JP 55135528A JP 13552880 A JP13552880 A JP 13552880A JP S5760596 A JPS5760596 A JP S5760596A
Authority
JP
Japan
Prior art keywords
final address
rom2
decoder
parity checking
address code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55135528A
Other languages
Japanese (ja)
Inventor
Takayuki Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55135528A priority Critical patent/JPS5760596A/en
Publication of JPS5760596A publication Critical patent/JPS5760596A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To increase the reliability and to reduce the cost of the device, by adding a decoder to an ROM and accordingly securing the detection for the final address of the ROM. CONSTITUTION:An address register 1 is reset when the power source of an electronic computer is applied or the automatic diagnosis mode is set. Then the microinstruction codes are read out successively to a parity checking circuit 3 from an ROM2 to carry out the parity check of the ROM2. At the same time, the readout microinstruction is transferred to a decoder 10 to be inspected whether it is the prescribed final address code or not. After this, the final address code is executed successively with each replace of the contents of the register 1. When the prescribed final address code is detected by the decoder 10, an FF9 is reset to complete the parity checking process of the ROM2.
JP55135528A 1980-09-29 1980-09-29 Parity checking system of control memory Pending JPS5760596A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55135528A JPS5760596A (en) 1980-09-29 1980-09-29 Parity checking system of control memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55135528A JPS5760596A (en) 1980-09-29 1980-09-29 Parity checking system of control memory

Publications (1)

Publication Number Publication Date
JPS5760596A true JPS5760596A (en) 1982-04-12

Family

ID=15153873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55135528A Pending JPS5760596A (en) 1980-09-29 1980-09-29 Parity checking system of control memory

Country Status (1)

Country Link
JP (1) JPS5760596A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01126740A (en) * 1987-11-11 1989-05-18 Nec Corp Pseudo circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01126740A (en) * 1987-11-11 1989-05-18 Nec Corp Pseudo circuit

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